X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Ftegra30-common.h;h=c2096fbe7ec497660f062bdc56498acbe364f1de;hb=084edbb6892b3712e2f9fd3abd5871652492fc42;hp=bfdbeb70d296691c2f3c087eca4e74f40aa4a04a;hpb=bd5053ffa5b8162257537bdb79ba829372423096;p=oweals%2Fu-boot.git diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index bfdbeb70d2..c2096fbe7e 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,33 +9,20 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" -/* Cortex-A9 uses a cache line size of 32 bytes */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * Errata configuration - */ -#define CONFIG_ARM_ERRATA_743622 -#define CONFIG_ARM_ERRATA_751472 - /* * NS16550 Configuration */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: @@ -61,10 +48,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" @@ -76,6 +64,5 @@ /* For USB EHCI controller */ #define CONFIG_EHCI_IS_TDI #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 -#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 #endif /* _TEGRA30_COMMON_H_ */