X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fspc1920.h;h=ea6a11237d2d06193c3569375e765da51b3123fe;hb=dca3b3d6d6396b67e5e84af53452164923c73443;hp=0b07a45d67414a35d4edd9dc0391a66a4f6e2910;hpb=9295acb77481cf099ef9b40e1fa2d145b3c7490c;p=oweals%2Fu-boot.git diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index 0b07a45d67..ea6a11237d 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -80,24 +80,24 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#ifndef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DATE \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PING \ - | CFG_CMD_DHCP \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) - /* & ~( CFG_CMD_NET)) */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII -#endif /* !CONFIG_COMMANDS */ +#undef CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -107,7 +107,7 @@ #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -202,7 +202,7 @@ /*----------------------------------------------------------------------- * I2C configuration */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ @@ -310,7 +310,7 @@ * FLASH timing: */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) + OR_SCY_6_CLK | OR_EHTR | OR_BI) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -361,14 +361,14 @@ * DSP Host Port Interface CS3 */ #define CFG_SPC1920_HPI_BASE 0x90000000 -#define CFG_PRELIM_OR3_AM 0xF0000000 +#define CFG_PRELIM_OR3_AM 0xF8000000 -#define CFG_OR3_PRELIM (CFG_PRELIM_OR3_AM | \ +#define CFG_OR3 (CFG_PRELIM_OR3_AM | \ OR_G5LS | \ OR_SCY_0_CLK | \ OR_BI) -#define CFG_BR3_PRELIM ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \ +#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \ BR_MS_UPMA | \ BR_PS_16 | \ BR_V); @@ -396,13 +396,13 @@ */ #define CFG_SPC1920_FRAM_BASE 0x80100000 #define CFG_PRELIM_OR4_AM 0xffff8000 -#define CFG_OR4_PRELIM (CFG_PRELIM_OR4_AM | \ +#define CFG_OR4 (CFG_PRELIM_OR4_AM | \ OR_ACS_DIV2 | \ OR_BI | \ OR_SCY_4_CLK | \ OR_TRLX) -#define CFG_BR4_PRELIM ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); +#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); /* * PLD CS5