X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fsorcery.h;h=f67898e840f817b62b0998cb716322e2d35d7fa0;hb=dc3e30bab7c5ef87bd24ebcbb7cdfc3fb2b44555;hp=dcb4092f29323e09e4fb645a4fc78bbe64a000af;hpb=3c2b3d454daa6024cc20d166b2f50efde169c7fe;p=oweals%2Fu-boot.git diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index dcb4092f29..f67898e840 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -31,19 +31,14 @@ #define CONFIG_MPC8220 1 #define CONFIG_SORCERY 1 /* Sorcery board */ -/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to - determine the CPU speed. */ -#define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ -#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */ +#define CONFIG_SYS_TEXT_BASE 0xfff00000 -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif +/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to + determine the CPU speed. */ +#define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ +#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */ /* * Serial console configuration @@ -51,32 +46,53 @@ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC */ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* PCI */ +#define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 + +#define CONFIG_PCI_MEM_BUS 0x80000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x71000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 + +#define CONFIG_PCI_CFG_BUS 0x70000000 +#define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS +#define CONFIG_PCI_CFG_SIZE 0x01000000 + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP | \ - 0) - -/* CFG_CMD_MII | \ */ -/* CFG_CMD_PCI | \ */ -/* CFG_CMD_USB | \ */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + /* * Default Environment @@ -85,7 +101,7 @@ #define CONFIG_HOSTNAME sorcery #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -112,21 +128,18 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_NET_MULTI +#define CONFIG_EEPRO100 /* * I2C configuration */ #define CONFIG_HARD_I2C 1 -#define CFG_I2C_MODULE 1 -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_MODULE 1 +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif +#define CONFIG_SYS_HUSH_PARSER /* * Flexbus Chipselect configuration @@ -136,109 +149,106 @@ */ /* Flash */ -#define CFG_CS0_BASE 0xf800 -#define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */ - -/* Workaround of hang-up after setting ctrl register for flash - After reset this register has value 0x003ffd80, which differs - from suggested only by the number of wait states. -#define CFG_CS0_CTRL 0x003f1580 -*/ +#define CONFIG_SYS_CS0_BASE 0xf800 +#define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */ +#define CONFIG_SYS_CS0_CTRL 0x001019c0 /* NVM */ -#define CFG_CS1_BASE 0xf100 -#define CFG_CS1_MASK 0x00080000 /* 512K */ -#define CFG_CS1_CTRL 0x003ffd40 /* 8bit port size? */ +#define CONFIG_SYS_CS1_BASE 0xf7e8 +#define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */ +#define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */ /* Atlas2 + Gemini */ -/* This CS# is mandatory? */ -#define CFG_CS2_BASE 0xf10A -#define CFG_CS2_MASK 0x00020000 /* 2x64K*/ -#define CFG_CS2_CTRL 0x003ffd00 /* 32bit port size? */ +#define CONFIG_SYS_CS2_BASE 0xf7e7 +#define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/ +#define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */ /* CAN Controller */ -/* This CS# is mandatory? */ -#define CFG_CS3_BASE 0xf10C -#define CFG_CS3_MASK 0x00010000 /* 64K */ -#define CFG_CS3_CTRL 0x003ffd40 /* 8Bit port size */ +#define CONFIG_SYS_CS3_BASE 0xf7e6 +#define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */ +#define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */ /* Foreign interface */ -#define CFG_CS4_BASE 0xF10D -#define CFG_CS4_MASK 0x00010000 /* 64K */ -#define CFG_CS4_CTRL 0x003ffd80 /* 16bit port size */ - -/* CPLD? */ -/* This CS# is mandatory? */ -#define CFG_CS5_BASE 0xF108 -#define CFG_CS5_MASK 0x00010000 -#define CFG_CS5_CTRL 0x003ffd80 /* 16bit port size */ +#define CONFIG_SYS_CS4_BASE 0xf7e5 +#define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */ +#define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */ -#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) -#define CFG_FLASH_BASE CFG_FLASH0_BASE +/* CPLD */ +#define CONFIG_SYS_CS5_BASE 0xf7e4 +#define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */ +#define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */ -#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks (actually 4? (at least 2)) */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip (actually 256) */ +#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16) +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define PHYS_AMD_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */ - -#define CFG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ - CFG_FLASH_BASE+0x04000000 } /* two banks */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */ /* * Environment settings */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH0_BASE) -#define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE -#define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000) +#define CONFIG_ENV_SIZE 0x4000 /* 16K */ +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_OVERWRITE 1 -#if defined CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_EEPROM -#elif defined CFG_ENV_IS_IN_EEPROM -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_IN_FLASH +#if defined CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_ENV_IS_IN_NVRAM +#undef CONFIG_ENV_IS_IN_EEPROM +#elif defined CONFIG_ENV_IS_IN_NVRAM +#undef CONFIG_ENV_IS_IN_FLASH +#undef CONFIG_ENV_IS_IN_EEPROM +#elif defined CONFIG_ENV_IS_IN_EEPROM +#undef CONFIG_ENV_IS_IN_NVRAM +#undef CONFIG_ENV_IS_IN_FLASH #endif /* * Memory map */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_SRAM_BASE (CFG_MBAR + 0x20000) -#define CFG_SRAM_SIZE 0x8000 +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 +#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000) +#define CONFIG_SYS_SRAM_SIZE 0x8000 /* Use SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) -#define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ +#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000) +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 #endif -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* SDRAM configuration (for SPD) */ -#define CFG_SDRAM_TOTAL_BANKS 1 -#define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ -#define CFG_SDRAM_SPD_SIZE 0x100 -#define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ +#define CONFIG_SYS_SDRAM_TOTAL_BANKS 1 +#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ +#define CONFIG_SYS_SDRAM_SPD_SIZE 0x100 +#define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ + +/* SDRAM drive strength register (for SSTL_2 class II)*/ +#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ + (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT)) /* * Ethernet configuration @@ -246,32 +256,43 @@ #define CONFIG_MPC8220_FEC 1 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ #define CONFIG_PHY_ADDR 0x1F +#define CONFIG_MII 1 /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Various low-level settings */ -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL 0 + +/* +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE +*/ #endif /* __CONFIG_H */