X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fsc520_cdp.h;h=0042e30057379bfcb6a9fcb8e91e066332ee8dda;hb=df4a0796e86662536df2387ddcf969c2a704bcc2;hp=e7d6c7942bafb46af6ec0ca2241c3b596545dce4;hpb=2262cfeef91458b01a1bfe3812ccbbfdf8b82807;p=oweals%2Fu-boot.git diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index e7d6c7942b..0042e30057 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -28,14 +28,17 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define GRUSS_TESTING /* * High Level Configuration Options * (easy to change) */ #define CONFIG_X86 1 /* This is a X86 CPU */ +#define CONFIG_SC520 1 /* Include support for AMD SC520 */ +#define CONFIG_ALI152X 1 /* Include support for Ali 152x SIO */ -#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ +#define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */ #define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ #define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */ @@ -60,35 +63,43 @@ /* * Size of malloc() pool */ -#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) +#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_BAUDRATE 9600 -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CFG_ENV_IS_NOWHERE 1 -#undef CFG_ENV_IS_IN_FLASH -#undef CFG_ENV_IS_IN_NVRAM -#undef CFG_ENV_IS_INEEPROM +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BAUDRATE 9600 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET) +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_PCI +#ifndef GRUSS_TESTING +#define CONFIG_CMD_SATA +#else +#undef CONFIG_CMD_SATA +#endif +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NET +#define CONFIG_CMD_EEPROM #define CONFIG_BOOTDELAY 15 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* */ - /* * Miscellaneous configurable options */ @@ -104,39 +115,58 @@ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x38000000 /* default load address */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1024 /* incrementer freq: 1kHz */ /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /*----------------------------------------------------------------------- * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */ - -#define PHYS_FLASH_1 0x38000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ - -#define CFG_FLASH_BASE PHYS_FLASH_1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x7a0000) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */ +#define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment in EEPROM */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +#define CONFIG_SPI +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/ +#define CONFIG_ENV_OFFSET 0 +#define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */ +#undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */ +#define CONFIG_SPI_X 1 + +/* + * JFFS2 partitions + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=SC520CDP Flash Bank #0" +#define MTDPARTS_DEFAULT "mtdparts=SC520CDP Flash Bank #0:-(jffs2)" +*/ /*----------------------------------------------------------------------- * Device drivers @@ -146,27 +176,22 @@ #define CONFIG_PCNET_79C973 #define CONFIG_PCNET_79C975 #define PCNET_HAS_PROM 1 -/************************************************************ - * IDE/ATA stuff - ************************************************************/ -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ - -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ - -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* reset for ide unsupported... */ -#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ /************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /* enable ATAPI Support */ +*SATA/Native Stuff +************************************************************/ +#ifndef GRUSS_TESTING +#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */ +#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ +#define CFG_SATA_MAX_DEVICE (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) +#define CONFIG_ATA_PIIX 1 /*Supports ata_piix driver */ +#else +#undef CFG_SATA_MAXBUS +#undef CFG_SATA_DEVS_PER_BUS +#undef CFG_SATA_MAX_DEVICE +#undef CONFIG_ATA_PIIX +#endif + /************************************************************ * DISK Partition support @@ -176,23 +201,15 @@ #define CONFIG_ISO_PARTITION /* Experimental */ /************************************************************ - * Keyboard support - ************************************************************/ -#define CONFIG_ISA_KEYBOARD - -#if 0 -/************************************************************ - * Video support + * Video/Keyboard support ************************************************************/ -#define CONFIG_VIDEO /*To enable video controller support */ -#define CONFIG_VIDEO_CT69000 -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ +#ifndef GRUSS_TESTING +#define CONFIG_VIDEO /* To enable video controller support */ +#else +#undef CONFIG_VIDEO #endif +#define CONFIG_I8042_KBD +#define CFG_ISA_IO 0 /************************************************************ * RTC @@ -203,8 +220,20 @@ /* * PCI stuff */ +#ifndef GRUSS_TESTING #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP /* pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW +#define CFG_FIRST_PCI_IRQ 10 +#define CFG_SECOND_PCI_IRQ 9 +#define CFG_THIRD_PCI_IRQ 11 +#define CFG_FORTH_PCI_IRQ 15 +#else +#undef CONFIG_PCI +#undef CONFIG_PCI_PNP +#undef CONFIG_PCI_SCAN_SHOW +#endif + + #endif /* __CONFIG_H */