X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap3_mvblx.h;h=b819d213408e7ac1ca1f14a937d707cebb359bfe;hb=a939ea3ab459d5fb3d1eaaec289c6ca85f2f74c1;hp=a0252a299921eb780b3462062cca5954b31f7bc4;hpb=84d7a0171f1abf8ef439298633fce325030b87b5;p=oweals%2Fu-boot.git

diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
index a0252a2999..b819d21340 100644
--- a/include/configs/omap3_mvblx.h
+++ b/include/configs/omap3_mvblx.h
@@ -37,7 +37,6 @@
 #define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_MVBLX		1	/* working with mvBlueLYNX-X */
 #define CONFIG_MACH_TYPE	MACH_TYPE_MVBLX
 
@@ -103,9 +102,6 @@
 #define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1
 
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR		1
-
 /* USB */
 #define CONFIG_MUSB_UDC			1
 #define CONFIG_USB_OMAP3		1
@@ -257,10 +253,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 #define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
-#endif
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -270,9 +262,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 #define CONFIG_ENV_IS_NOWHERE	1
 
 /*----------------------------------------------------------------------------
@@ -280,7 +269,6 @@
  *----------------------------------------------------------------------------
  */
 #if defined(CONFIG_CMD_NET)
-  #define CONFIG_NET_MULTI
   #define CONFIG_SMC911X		1
   #define CONFIG_SMC911X_32_BIT
   #define CONFIG_SMC911X_BASE     0x2C000000
@@ -310,4 +298,6 @@
 
 #define CONFIG_OMAP3_SPI
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif /* __CONFIG_H */