X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fmpc5121ads.h;h=3740316d6b9be54f48586c26aa54cf6bbc3e1880;hb=abaa5ba4e3b52f82b8158044cba6cf7986309d43;hp=76f174db3fa57849adebf7dea7c287555c13448a;hpb=7d4450a9773673052fcd7fdf0a4a88c089126ac1;p=oweals%2Fu-boot.git

diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 76f174db3f..3740316d6b 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -47,14 +47,16 @@
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
 #define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
-#undef CONFIG_FSL_DIU_LOGO_BMP		/* Don't include FSL DIU binary bmp */
 
 /* video */
 #undef CONFIG_VIDEO
 
-#if defined(CONFIG_VIDEO)
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
 #endif
 
 /* CONFIG_PCI is defined at config time */
@@ -85,6 +87,9 @@
 #endif
 #define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
 
 /* DDR Controller Configuration
  *
@@ -131,28 +136,55 @@
  *	[04:00] DRAM tRPA
  */
 #ifdef CONFIG_MPC5121ADS_REV2
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xE8604A00
 #define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
 #define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
 #else
-#define CONFIG_SYS_MDDRC_SYS_CFG	 0xFA804A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	 0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34310864
 #endif
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
-
-#define CONFIG_SYS_MICRON_NOP		0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
-#define CONFIG_SYS_MICRON_EM2		0x01020000
-#define CONFIG_SYS_MICRON_EM3		0x01030000
-#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
-#define CONFIG_SYS_MICRON_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x06183D2E
+
+#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA	 	0xEA802B00
+#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA	0x690e1189
+#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA	0x35310864
+
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
+#define CONFIG_SYS_DDRCMD_EM2		0x01020000
+#define CONFIG_SYS_DDRCMD_EM3		0x01030000
+#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
+
+#define DDRCMD_EMR_OCD(pr, ohm) ( \
+	(1 << 24)	   | /* MDDRC Command Request	*/ \
+	(1 << 16)	   | /* MODE Reg BA[2:0] 	*/ \
+	(0 << 12)	   | /* Outputs 0=Enabled	*/ \
+	(0 << 11)	   | /* RDQS 			*/ \
+	(1 << 10)	   | /* DQS# 			*/ \
+	(pr <<  7)	   | /* OCD prog 7=deflt,0=exit	*/ \
+		    /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
+	((ohm & 0x2) <<  5)| /* Rtt1			*/ \
+	(0 <<  3)	   | /* additive posted CAS#	*/ \
+	((ohm & 0x1) <<  2)| /* Rtt0			*/ \
+	(0 <<  0)	   | /* Output Drive Strength	*/ \
+	(0 <<  0))	     /* DLL Enable 0=Normal	*/
+
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	DDRCMD_EMR_OCD(7, 0)
+#define CONFIG_SYS_ELPIDA_OCD_EXIT	DDRCMD_EMR_OCD(0, 0)
+
+#define DDRCMD_MODE_REG(cas, wr) ( \
+	(1 << 24)    | /* MDDRC Command Request			*/ \
+	(0 << 16)    | /* MODE Reg BA[2:0] 			*/ \
+	((wr-1) << 9)| /* Write Recovery 			*/ \
+	(cas << 4)   | /* CAS 					*/ \
+	(0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved	*/ \
+	(2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8	*/
+
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	DDRCMD_MODE_REG(3, 3)
+#define CONFIG_SYS_ELPIDA_INIT_DEV_OP	DDRCMD_MODE_REG(4, 4)
+#define CONFIG_SYS_ELPIDA_RES_DLL	(DDRCMD_MODE_REG(4, 4) | (1 << 8))
 
 /* DDR Priority Manager Configuration */
 #define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
@@ -212,8 +244,6 @@
 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
 #define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
 
-#define	CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
-
 /*
  * Configuration parameters for MPC5121 NAND driver
  */
@@ -256,7 +286,6 @@
  * Serial Port
  */
 #define CONFIG_CONS_INDEX     1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
 
 /*
  * Serial console configuration
@@ -449,10 +478,10 @@
 
 /*
  * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
 
 /* Cache Configuration */
 #define CONFIG_SYS_DCACHE_SIZE		32768