X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fml401.h;h=7e0df870191871e690f31053a437d56473658311;hb=9939ffd5fbf1f5aff4d8172531d4fc33797c62c8;hp=4dc2afc63dd3a6830f38470949dc3f152ffd5d6e;hpb=76316a318de91f6184e7c22a10e02d275ade2441;p=oweals%2Fu-boot.git diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 4dc2afc63d..7e0df87019 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -1,7 +1,7 @@ /* - * (C) Copyright 2007 Czech Technical University. + * (C) Copyright 2007-2008 Michal Simek * - * Michal SIMEK + * Michal SIMEK * * See file CREDITS for list of people who contributed to this * project. @@ -28,31 +28,75 @@ #include "../board/xilinx/ml401/xparameters.h" #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ +#define MICROBLAZE_V5 1 #define CONFIG_ML401 1 /* ML401 Board */ /* uart */ -#define CONFIG_SERIAL_BASE CONFIG_XILINX_UARTLITE_0_BASEADDR -#define CONFIG_BAUDRATE CONFIG_XILINX_UARTLITE_0_BAUDRATE +#ifdef XILINX_UARTLITE_BASEADDR +#define CONFIG_XILINX_UARTLITE +#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR +#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE #define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE } +#else +#ifdef XILINX_UART16550_BASEADDR +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550_COM1 XILINX_UART16550_BASEADDR +#define CFG_NS16550_CLK XILINX_UART16550_CLOCK_HZ +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 115200 } +#endif +#endif /* setting reset address */ -#define CFG_RESET_ADDRESS TEXT_BASE +/*#define CFG_RESET_ADDRESS TEXT_BASE*/ + +/* ethernet */ +#ifdef XILINX_EMAC_BASEADDR +#define CONFIG_XILINX_EMAC 1 +#define CFG_ENET +#else +#ifdef XILINX_EMACLITE_BASEADDR +#define CONFIG_XILINX_EMACLITE 1 +#define CFG_ENET +#endif +#endif +#undef ET_DEBUG /* gpio */ +#ifdef XILINX_GPIO_BASEADDR #define CFG_GPIO_0 1 -#define CFG_GPIO_0_ADDR CONFIG_XILINX_GPIO_0_BASEADDR +#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR +#endif /* interrupt controller */ +#ifdef XILINX_INTC_BASEADDR #define CFG_INTC_0 1 -#define CFG_INTC_0_ADDR CONFIG_XILINX_INTC_0_BASEADDR -#define CFG_INTC_0_NUM CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS +#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR +#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS +#endif /* timer */ +#ifdef XILINX_TIMER_BASEADDR +#if (XILINX_TIMER_IRQ != -1) #define CFG_TIMER_0 1 -#define CFG_TIMER_0_ADDR CONFIG_XILINX_TIMER_0_BASEADDR -#define CFG_TIMER_0_IRQ CONFIG_XILINX_TIMER_0_IRQ -#define FREQUENCE 66666666 +#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR +#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ +#define FREQUENCE XILINX_CLOCK_FREQ #define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 ) +#endif +#else +#ifdef XILINX_CLOCK_FREQ +#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ +#else +#error BAD CLOCK FREQ +#endif +#endif +/* FSL */ +/* #define CFG_FSL_2 */ +/* #define FSL_INTR_2 1 */ /* * memory layout - Example @@ -62,6 +106,7 @@ * * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000 * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000 + * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 * * 0x1000_0000 CFG_SDRAM_BASE * FREE @@ -71,28 +116,33 @@ * FREE * * STACK + * 0x13F7_F000 CFG_MALLOC_BASE + * MALLOC_AREA 256kB Alloc * 0x11FB_F000 CFG_MONITOR_BASE - * MONITOR_CODE + * MONITOR_CODE 256kB Env * 0x13FF_F000 CFG_GBL_DATA_OFFSET - * GLOBAL_DATA + * GLOBAL_DATA 4kB bd, gd * 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE */ /* ddr sdram - main memory */ -#define CFG_SDRAM_BASE CONFIG_XILINX_ERAM_START -#define CFG_SDRAM_SIZE CONFIG_XILINX_ERAM_SIZE +#define CFG_SDRAM_BASE XILINX_RAM_START +#define CFG_SDRAM_SIZE XILINX_RAM_SIZE #define CFG_MEMTEST_START CFG_SDRAM_BASE #define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000) /* global pointer */ #define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */ -#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */ +/* start of global data */ +#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 #define CFG_MONITOR_LEN SIZE #define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN) +#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_MALLOC_LEN SIZE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) /* stack */ #define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE @@ -101,13 +151,14 @@ #define FLASH #ifdef FLASH - #define CFG_FLASH_BASE CONFIG_XILINX_FLASH_START - #define CFG_FLASH_SIZE CONFIG_XILINX_FLASH_SIZE + #define CFG_FLASH_BASE XILINX_FLASH_START + #define CFG_FLASH_SIZE XILINX_FLASH_SIZE #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + #define CFG_FLASH_PROTECTION /* hardware flash protection */ #ifdef RAMENV #define CFG_ENV_IS_NOWHERE 1 @@ -116,9 +167,9 @@ #else /* !RAMENV */ #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR 0x40000 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CFG_ENV_SIZE 0x2000 + #define CFG_ENV_ADDR (CFG_FLASH_BASE + (2 * CFG_ENV_SECT_SIZE)) + #define CFG_ENV_SIZE 0x40000 #endif /* !RAMBOOT */ #else /* !FLASH */ /* ENV in RAM */ @@ -126,69 +177,72 @@ #define CFG_ENV_IS_NOWHERE 1 #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) + #define CFG_FLASH_PROTECTION /* hardware flash protection */ #endif /* !FLASH */ -#ifdef FLASH - #ifdef RAMENV - #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ - CFG_CMD_MEMORY |\ - CFG_CMD_MISC |\ - CFG_CMD_AUTOSCRIPT |\ - CFG_CMD_IRQ |\ - CFG_CMD_ASKENV |\ - CFG_CMD_BDI |\ - CFG_CMD_RUN |\ - CFG_CMD_LOADS |\ - CFG_CMD_LOADB |\ - CFG_CMD_IMI |\ - CFG_CMD_NET |\ - CFG_CMD_CACHE |\ - CFG_CMD_IMLS |\ - CFG_CMD_FLASH |\ - CFG_CMD_PING \ - ) - #else /* !RAMENV */ - #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ - CFG_CMD_MEMORY |\ - CFG_CMD_MISC |\ - CFG_CMD_AUTOSCRIPT |\ - CFG_CMD_IRQ |\ - CFG_CMD_ASKENV |\ - CFG_CMD_BDI |\ - CFG_CMD_RUN |\ - CFG_CMD_LOADS |\ - CFG_CMD_LOADB |\ - CFG_CMD_IMI |\ - CFG_CMD_NET |\ - CFG_CMD_CACHE |\ - CFG_CMD_IMLS |\ - CFG_CMD_FLASH |\ - CFG_CMD_PING |\ - CFG_CMD_ENV |\ - CFG_CMD_SAVES \ - ) +/* system ace */ +#ifdef XILINX_SYSACE_BASEADDR + #define CONFIG_SYSTEMACE + /* #define DEBUG_SYSTEMACE */ + #define SYSTEMACE_CONFIG_FPGA + #define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR + #define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH + #define CONFIG_DOS_PARTITION +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MFSL + +#ifndef CFG_ENET + #undef CONFIG_CMD_NET +#else + #define CONFIG_CMD_PING +#endif + +#if defined(CONFIG_SYSTEMACE) + #define CONFIG_CMD_EXT2 + #define CONFIG_CMD_FAT +#endif + +#if defined(FLASH) + #define CONFIG_CMD_ECHO + #define CONFIG_CMD_FLASH + #define CONFIG_CMD_IMLS + #define CONFIG_CMD_JFFS2 + + #if !defined(RAMENV) + #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVES #endif +#else + #undef CONFIG_CMD_FLASH +#endif + +#if defined(CONFIG_CMD_JFFS2) +/* JFFS2 partitions */ +#define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ +#define MTDIDS_DEFAULT "nor0=ml401-0" -#else /* !FLASH */ - #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ - CFG_CMD_MEMORY |\ - CFG_CMD_MISC |\ - CFG_CMD_AUTOSCRIPT |\ - CFG_CMD_IRQ |\ - CFG_CMD_ASKENV |\ - CFG_CMD_BDI |\ - CFG_CMD_RUN |\ - CFG_CMD_LOADS |\ - CFG_CMD_LOADB |\ - CFG_CMD_IMI |\ - CFG_CMD_NET |\ - CFG_CMD_CACHE |\ - CFG_CMD_PING \ - ) -#endif /* !FLASH */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* default mtd partition table */ +#define MTDPARTS_DEFAULT "mtdparts=ml401-0:256k(u-boot),"\ + "256k(env),3m(kernel),1m(romfs),"\ + "1m(cramfs),-(jffs2)" +#endif /* Miscellaneous configurable options */ #define CFG_PROMPT "U-Boot-mONStR> " @@ -198,24 +252,28 @@ #define CFG_LONGHELP #define CFG_LOAD_ADDR 0x12000000 /* default load address */ -#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTDELAY 30 #define CONFIG_BOOTARGS "root=romfs" #define CONFIG_HOSTNAME "ml401" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" +#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.5 -#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.5 +#define CONFIG_GATEWAYIP 192.168.0.1 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD /* architecture dependent code */ #define CFG_USR_EXCEP /* user exception */ #define CFG_HZ 1000 -/* system ace */ -/*#define CONFIG_SYSTEMACE -#define DEBUG_SYSTEMACE -#define CFG_SYSTEMACE_BASE 0xCF000000 -#define CFG_SYSTEMACE_WIDTH 8 -#define CONFIG_DOS_PARTITION -*/ +#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" + +#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ + "nor0=ml401-0\0"\ + "mtdparts=mtdparts=ml401-0:"\ + "256k(u-boot),256k(env),3m(kernel),"\ + "1m(romfs),1m(cramfs),-(jffs2)\0" + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_OF_LIBFDT 1 + #endif /* __CONFIG_H */