X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Flwmon5.h;h=a6f2864c6593733f57a8738b10aa534287ab5f0d;hb=385488dc1b20e55739cfdecdce20319a60dbad44;hp=d00371012507a78bc1dd6fb651d7738da78d1f07;hpb=083d506937002f2795c80fe0c3ae194ad2c3d085;p=oweals%2Fu-boot.git

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index d003710125..a6f2864c65 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -43,6 +43,8 @@
 
 #define CONFIG_SYS_CLK_FREQ	33300000	/* external freq to pll	*/
 
+#define CONFIG_4xx_DCACHE		/* enable cache in SDRAM	*/
+
 #define CONFIG_BOARD_EARLY_INIT_F	/* Call board_early_init_f	*/
 #define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r	*/
 #define CONFIG_BOARD_POSTCLK_INIT	/* Call board_postclk_init	*/
@@ -87,10 +89,9 @@
  */
 #define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
-#define CONFIG_SYS_INIT_RAM_END		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes initial data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 /* unused GPT0 COMP reg	*/
 #define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
@@ -193,6 +194,17 @@
 #define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
 			CONFIG_SYS_NS16550_COM2 }
 
+#define CONFIG_POST_UART  {				\
+	"UART test",					\
+	"uart",						\
+	"This test verifies the UART operation.",	\
+	POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,	\
+	&uart_post_test,				\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_UART				\
+	}
+
 #define CONFIG_POST_WATCHDOG  {				\
 	"Watchdog timer test",				\
 	"watchdog",					\
@@ -295,14 +307,13 @@
 #define CONFIG_SYS_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard		*/
 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* PIC I/O addr               */
 
-#define I2C_ADDR_LIST	{						\
-			CONFIG_SYS_I2C_RTC_ADDR,			\
-			CONFIG_SYS_I2C_EEPROM_CPU_ADDR,			\
-			CONFIG_SYS_I2C_EEPROM_MB_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_2_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,			\
-			CONFIG_SYS_I2C_DSPIC_IO_ADDR }
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
+					 CONFIG_SYS_I2C_EEPROM_MB_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_2_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
+					 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
 
 /*
  * Pass open firmware flat tree
@@ -312,6 +323,8 @@
 /* Update size in "reg" property of NOR FLASH device tree nodes */
 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 
+#define CONFIG_FIT			/* enable FIT image support	*/
+
 #define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
 
 #define	CONFIG_PREBOOT		"setenv bootdelay 15"
@@ -366,7 +379,6 @@
 #define CONFIG_HAS_ETH0
 #define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
 
-#define CONFIG_NET_MULTI	1
 #define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
 #define CONFIG_PHY1_ADDR	1
 
@@ -384,16 +396,18 @@
 #define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_SPLASH_SCREEN
 
-/* USB */
-#ifdef CONFIG_440EPX
-#define CONFIG_USB_OHCI
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
+#define CONFIG_USB_EHCI_PPC4XX		/* on PPC4xx platform		*/
+#define CONFIG_SYS_PPC4XX_USB_ADDR	0xe0000300
+#define CONFIG_EHCI_DCACHE		/* with dcache handling support	*/
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
 #define CONFIG_USB_STORAGE
 
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-#endif /* CONFIG_440EPX */
-
 /* Partitions */
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -425,7 +439,6 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
@@ -473,22 +486,6 @@
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI			/* include pci support	        */
-#undef CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
-#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
-
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
-#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
-
 #ifndef DEBUG
 #define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
 #endif