X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fls2080aqds.h;h=8ab892b5c3fa7094748b9695739c778ad64384b1;hb=b9da77f1958aab4ec50ff2f095b40464ca2489dd;hp=dcd1b0c35c5e5db0f1935f0c0d8431c6b55a183d;hpb=390194d43fa4478ddb638164ddb114c979f3e57a;p=oweals%2Fu-boot.git diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index dcd1b0c35c..8ab892b5c3 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -1,8 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017, 2019-2020 NXP * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LS2_QDS_H @@ -16,9 +15,10 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FSL_QSPI -#undef CONFIG_CMD_IMLS #define CONFIG_QIXIS_I2C_ACCESS +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C_EARLY_INIT +#endif #define CONFIG_SYS_I2C_IFDR_DIV 0x7e #endif @@ -44,11 +44,8 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 #endif -#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 @@ -59,7 +56,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) @@ -100,9 +99,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -228,16 +224,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_ENV_OFFSET (896 * 1024) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x20000 #endif #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT @@ -267,12 +258,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#ifndef CONFIG_QSPI_BOOT -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 -#endif #endif /* Debug Server firmware */ @@ -292,8 +277,6 @@ unsigned long get_board_ddr_clk(void); /* SPI */ #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) -#define CONFIG_SPI_FLASH - #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_SST @@ -327,7 +310,9 @@ unsigned long get_board_ddr_clk(void); */ #define RTC #define CONFIG_RTC_DS3231 1 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT #define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT /* EEPROM */ #define CONFIG_ID_EEPROM @@ -346,13 +331,12 @@ unsigned long get_board_ddr_clk(void); /* MMC */ #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ @@ -365,10 +349,74 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "mcmemsize=0x40000000\0" \ - "mcinitcmd=esbc_validate 0x580700000;" \ - "esbc_validate 0x580740000;" \ + "mcinitcmd=esbc_validate 0x580640000;" \ + "esbc_validate 0x580680000;" \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" +#else +#ifdef CONFIG_TFABOOT +#define SD_MC_INIT_CMD \ + "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" +#define IFC_MC_INIT_CMD \ + "fsl_mc start mc 0x580a00000" \ + " 0x580e00000 \0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "loadaddr_sd=0x90100000\0" \ + "kernel_addr=0x581000000\0" \ + "kernel_addr_sd=0x8000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581000000\0" \ + "kernel_start_sd=0x8000\0" \ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_size_sd=0x14000\0" \ + "load_addr=0xa0000000\0" \ + "kernelheader_addr=0x580600000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernelheader_size=0x40000\0" \ + "BOARD=ls2088aqds\0" \ + "mcmemsize=0x70000000 \0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + IFC_MC_INIT_CMD \ + BOOTENV \ + "boot_scripts=ls2088aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "nor_bootcmd=echo Trying load from nor..;" \ + "cp.b $kernel_addr $load_addr " \ + "$kernel_size ; env exists secureboot && " \ + "cp.b $kernelheader_addr $kernelheader_addr_r " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + "bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "bootm $load_addr#$BOARD\0" #elif defined(CONFIG_SD_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -400,15 +448,37 @@ unsigned long get_board_ddr_clk(void); "mcmemsize=0x40000000\0" \ "mcinitcmd=fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" -#endif /* CONFIG_SECURE_BOOT */ - +#endif /* CONFIG_TFABOOT */ +#endif /* CONFIG_NXP_ESBC */ + +#ifdef CONFIG_TFABOOT +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) +#include + +#define SD_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \ + "&& esbc_validate $load_addr; " \ + "env exists mcinitcmd && run mcinitcmd " \ + "&& mmc read 0x80d00000 0x6800 0x800 " \ + "&& fsl_mc lazyapply dpl 0x80d00000; " \ + "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" + +#define IFC_NOR_BOOTCOMMAND \ + "env exists mcinitcmd && env exists secureboot "\ + "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\ + "&& fsl_mc lazyapply dpl 0x580d00000;" \ + "run distro_bootcmd;run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) #define CONFIG_FSL_MEMAC -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS #define SGMII_CARD_PORT1_PHY_ADDR 0x1C #define SGMII_CARD_PORT2_PHY_ADDR 0x1d #define SGMII_CARD_PORT3_PHY_ADDR 0x1E @@ -431,18 +501,10 @@ unsigned long get_board_ddr_clk(void); #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf -#define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "DPMAC1@xgmii" #endif -/* - * USB - */ -#define CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - #include #endif /* __LS2_QDS_H */