X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fcorvus.h;h=ace511f76534bc9188a2222eee32a0f15cb2bc0f;hb=7f30f4b5b285cb91e1e25b5b61a04beabe8c470b;hp=11ba4cffc4442e0787b3a282a29af6e5c965c369;hpb=a891601ce51edbafa1a2750c96a618e4fcbca1c2;p=oweals%2Fu-boot.git

diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 11ba4cffc4..ace511f765 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -18,6 +18,8 @@
 
 #define MACH_TYPE_CORVUS               2066
 
+#define CONFIG_MACH_TYPE		MACH_TYPE_CORVUS
+#define CONFIG_SYS_GENERIC_BOARD
 /*
  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  * adapting the initial boot program.
@@ -25,17 +27,13 @@
  * hex number here!
  */
 
-#define CONFIG_SYS_TEXT_BASE  0x73f00000
+#define CONFIG_SYS_TEXT_BASE  0x72000000
 
-#define CONFIG_AT91_LEGACY
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
-#define CONFIG_SYS_HZ		        1000
-
-#define CONFIG_AT91FAMILY
 
 #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS
@@ -110,7 +108,6 @@
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
 #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
-
 #endif
 
 /* Ethernet */
@@ -161,5 +158,52 @@
  */
 #define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + \
 				128*1024, 0x1000)
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		(12 * 1024)
+#define CONFIG_SPL_STACK		(16 * 1024)
+
+#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_BSS_MAX_SIZE		(2 * 1024)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define AT91_PLL_LOCK_TIMEOUT		1000000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#define ATMEL_BASE_MPDDRC		ATMEL_BASE_DDRSDRC0
 
 #endif