X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2Fcaddy2.h;h=15ac17985f39bf644503281ce3aedb0e41351bc6;hb=eb53a18c9e903e35e8e8d52da96c33b63822881c;hp=ffd52a200a32c2ae2c640432e2c830c7175e89bf;hpb=5d2f4c9641bae821d421a3d362596f84905daca2;p=oweals%2Fu-boot.git

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
index ffd52a200a..15ac17985f 100644
--- a/include/configs/caddy2.h
+++ b/include/configs/caddy2.h
@@ -25,8 +25,6 @@
 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
 #undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
 
-#define CONFIG_SYS_IMMR		0xE0000000
-
 #undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
 #define CONFIG_SYS_MEMTEST_END		0x00100000
@@ -53,9 +51,7 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* DDR is sys memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
 					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 #define CONFIG_DDR_2T_TIMING
@@ -69,31 +65,10 @@
  */
 #define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */
-#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
-					 BR_PS_16 |	/*  16bit */ \
-					 BR_MS_GPCM |	/*  MSEL = GPCM */ \
-					 BR_V)		/* valid */
-
-#define CONFIG_SYS_OR0_PRELIM		(OR_AM_4MB \
-					| OR_GPCM_XAM \
-					| OR_GPCM_CSNT \
-					| OR_GPCM_ACS_DIV2 \
-					| OR_GPCM_XACS \
-					| OR_GPCM_SCY_15 \
-					| OR_GPCM_TRLX_SET \
-					| OR_GPCM_EHTR_SET \
-					| OR_GPCM_EAD)
-					/* 0xffc06ff7 */
+
 
 #define CONFIG_SYS_WINDOW1_BASE		0xf0000000
-#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_WINDOW1_BASE \
-					| BR_PS_32 \
-					| BR_MS_GPCM \
-					| BR_V)
-					/* 0xF0001801 */
-#define CONFIG_SYS_OR1_PRELIM		(OR_AM_256KB \
-					| OR_GPCM_SETA)
-					/* 0xfffc0208 */
+
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/
@@ -121,15 +96,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
 
 /*
@@ -284,12 +250,6 @@
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE)
-
-#define CONFIG_SYS_HID2		HID2_HBE
-
 #define CONFIG_SYS_GPIO1_PRELIM
 #define CONFIG_SYS_GPIO1_DIR	0x00100000
 #define CONFIG_SYS_GPIO1_DAT	0x00100000