X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FVCMA9.h;h=df6894f3240a69451890281289d6e3e9c3e5b1b7;hb=2eb6e01049886bdaadf11243e7c8cf674c34ed0b;hp=a73281c02f71a91ab98b1941f5fe0d41531084fc;hpb=1cb8e980c41e86760fa93de63f4e4cf643bef9d9;p=oweals%2Fu-boot.git diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index a73281c02f..df6894f324 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002, 2003 * Sysgo Real-Time Solutions, GmbH * Marius Groeger * Gary Jennejohn @@ -29,12 +29,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * If we are developing, we might want to start armboot from ram - * so we MUST NOT initialize critical regs like mem-timing ... - */ -#define CONFIG_INIT_CRITICAL /* undef for developing */ - /* * High Level Configuration Options * (easy to change) @@ -42,6 +36,7 @@ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ @@ -53,20 +48,33 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_REGINFO | \ - CFG_CMD_ELF | \ - CFG_CMD_BSP) - -/* this must be included after the definiton of CONFIG_COMMANDS */ -#include + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_FAT +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP + #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " @@ -92,10 +100,11 @@ /* * Size of malloc() pool */ -#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) +/*#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)*/ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_MONITOR_LEN (256 * 1024) -#define CFG_MALLOC_LEN (128 * 1024) +#define CFG_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ /* * Hardware drivers @@ -111,17 +120,38 @@ */ #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +/************************************************************ + * USB support + ************************************************************/ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 + +/* Enable needed helper functions */ +#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ + +/************************************************************ + * RTC + ************************************************************/ +#define CONFIG_RTC_S3C24X0 1 + + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 5 +/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ + #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 10.0.0.110 #define CONFIG_SERVERIP 10.0.0.1 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ @@ -138,9 +168,10 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_MEMTEST_START 0x30000000 /* memtest works on */ -#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ +#define CFG_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ + #define CFG_ALT_MEMTEST -#define CFG_LOAD_ADDR 0x33000000 /* default load address */ +#define CFG_LOAD_ADDR 0x30800000 /* default load address */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ @@ -152,6 +183,16 @@ /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* support BZIP2 compression */ +#define CONFIG_BZIP2 1 + +/************************************************************ + * Ident + ************************************************************/ +/*#define VERSION_TAG "released"*/ +#define VERSION_TAG "unstable" +#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG + /*----------------------------------------------------------------------- * Stack sizes * @@ -168,8 +209,6 @@ */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define CFG_FLASH_BASE PHYS_FLASH_1 @@ -204,6 +243,49 @@ #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ #endif -#define MULTI_PURPOSE_SOCKET_ADDR 0 + +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 + +#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 + +/*----------------------------------------------------------------------- + * NAND flash settings + */ +#if defined(CONFIG_CMD_NAND) + +#define CFG_NAND_LEGACY +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_WAIT_READY(nand) NF_WaitRB() + +#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) +#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW) + + +#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d) +#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d) +#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d) +#define WRITE_NAND(d, adr) NF_Write(d) +#define READ_NAND(adr) NF_Read() +/* the following functions are NOP's because S3C24X0 handles this in hardware */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) + +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_MTD_NAND_ECC_JFFS2 1 + +#endif #endif /* __CONFIG_H */