X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FTQM85xx.h;h=2ef24cd7e506603e5b0fd825c1d5fe5d135c0ee6;hb=2c5bd16af132bb6e9158c43fc6206fa0f1f501c1;hp=6a48d8f7d91947993a52ed61eaa8babe51156221;hpb=ad7ee5d43b0db94079d56521dabca25674f28747;p=oweals%2Fu-boot.git

diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 6a48d8f7d9..2ef24cd7e5 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -41,12 +41,14 @@
 #define CONFIG_E500		1	/* BOOKE e500 family		*/
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
 
-#if defined(CONFIG_TQM8548_BE)
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
 #define CONFIG_TQM8548
 #endif
 
 #define CONFIG_PCI
+#ifndef CONFIG_TQM8548_AG
 #define CONFIG_PCI1			/* PCI/PCI-X controller		*/
+#endif
 #ifdef CONFIG_TQM8548
 #define CONFIG_PCIE1			/* PCI Express interface	*/
 #endif
@@ -88,7 +90,7 @@
 
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code	*/
 
-#ifdef CONFIG_TQM8548_BE
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
 #define	CONFIG_CAN_DRIVER		/* CAN Driver support		*/
 #endif
 
@@ -144,6 +146,9 @@
  */
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#ifdef CONFIG_TQM8548_AG
+#define CONFIG_VERY_BIG_RAM
+#endif
 
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
@@ -366,35 +371,17 @@
 #define	CONFIG_SYS_NAND_CS_DIST	0x200
 
 #define CONFIG_SYS_NAND_SIZE		0x8000
-#define CONFIG_SYS_NAND0_BASE		(CONFIG_SYS_CCSRBAR + 0x03010000)
-#define CONFIG_SYS_NAND1_BASE		(CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND2_BASE		(CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
-#define CONFIG_SYS_NAND3_BASE		(CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE     2	/* Max number of NAND devices	*/
-
-#if (CONFIG_SYS_MAX_NAND_DEVICE == 1)
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 2)
-#define	CONFIG_SYS_NAND_QUIET_TEST	1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-			     CONFIG_SYS_NAND1_BASE, \
-}
-#elif (CONFIG_SYS_MAX_NAND_DEVICE == 4)
-#define	CONFIG_SYS_NAND_QUIET_TEST	1
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
-			     CONFIG_SYS_NAND1_BASE, \
-			     CONFIG_SYS_NAND2_BASE, \
-			     CONFIG_SYS_NAND3_BASE, \
-}
-#endif
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_CCSRBAR + 0x03010000)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
+#define CONFIG_SYS_NAND_MAX_CHIPS	2	/* Number of chips per device	*/
 
 /* CS3 for NAND Flash */
-#define CONFIG_SYS_BR3_PRELIM		((CONFIG_SYS_NAND0_BASE & BR_BA) | BR_PS_8 | \
-				 BR_MS_UPMB | BR_V)
+#define CONFIG_SYS_BR3_PRELIM		((CONFIG_SYS_NAND_BASE & BR_BA) | \
+					 BR_PS_8 | BR_MS_UPMB | BR_V)
 #define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
 
-#define NAND_BIG_DELAY_US       25	/* max tR for Samsung devices	*/
+#define NAND_BIG_DELAY_US		25	/* max tR for Samsung devices	*/
 
 #endif /* CONFIG_NAND */
 
@@ -592,14 +579,14 @@
 
 #define	CONFIG_JFFS2_NAND	1
 
-#ifdef CONFIG_JFFS2_CMDLINE
+#ifdef CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT		"nand0=TQM85xx-nand"
 #define MTDPARTS_DEFAULT	"mtdparts=TQM85xx-nand:-"
 #else
 #define CONFIG_JFFS2_DEV 	"nand0"	/* NAND device jffs2 lives on	*/
 #define CONFIG_JFFS2_PART_OFFSET 0	/* start of jffs2 partition	*/
 #define CONFIG_JFFS2_PART_SIZE	0x200000 /* size of jffs2 partition	*/
-#endif /* CONFIG_JFFS2_CMDLINE */
+#endif /* CONFIG_CMD_MTDPARTS */
 
 #endif /* CONFIG_NAND */
 
@@ -613,7 +600,9 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SNTP
+#ifndef CONFIG_TQM8548_AG
 #define CONFIG_CMD_DATE
+#endif
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_MII