X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FRPXClassic.h;h=706e2aadc7a8b09ef09dd95ea7cd464225907bc5;hb=9939ffd5fbf1f5aff4d8172531d4fc33797c62c8;hp=f20b8f99ac123f9ebb336b869506e993d75f961f;hpb=a6c7ad2f65afaa717ba19cbf9d8d138b5f10ccf9;p=oweals%2Fu-boot.git

diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
index f20b8f99ac..706e2aadc7 100644
--- a/include/configs/RPXClassic.h
+++ b/include/configs/RPXClassic.h
@@ -78,9 +78,9 @@
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
@@ -88,15 +88,26 @@
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
 
 #define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
 
 
-#define CONFIG_COMMANDS	(CFG_CMD_ALL & ~CFG_CMD_NONSTD | CFG_CMD_ELF)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
 
 /*
  * Miscellaneous configurable options
@@ -104,7 +115,7 @@
 #define CFG_RESET_ADDRESS	0x80000000
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
@@ -182,7 +193,7 @@
 #define	CFG_SDRAM_BASE		0x00000000
 #define CFG_FLASH_BASE	0xFF000000
 
-#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) 
+#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
 #define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #else
 #define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
@@ -222,7 +233,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
@@ -331,8 +342,7 @@
  *
  */
 /* #define	CFG_DER	0x2002000F */
-/* #define CFG_DER	0 */
-#define	CFG_DER	0x0082000F
+#define CFG_DER	0
 
 /*
  * Init Memory Controller:
@@ -370,8 +380,8 @@
 
 /* ECCX CS settings                                                          */
 #define SED13806_OR             0xFFC00108     /* - 4 Mo
-                                                   - Burst inhibit
-                                                   - external TA             */
+						   - Burst inhibit
+						   - external TA             */
 #define SED13806_REG_ADDR       0xa0000000
 #define SED13806_ACCES          0x801           /* 16 bit access             */
 
@@ -391,8 +401,8 @@
 
 /* Definitions for CSR8                                                      */
 #define ECCX_ENEPSON            0x80    /* Bit 0:
-                                           0= disable and reset SED1386
-                                           1= enable SED1386                 */
+					   0= disable and reset SED1386
+					   1= enable SED1386                 */
 /* Bit 1:   0= SED1386 in Big Endian mode                                    */
 /*          1= SED1386 in little endian mode                                 */
 #define ECCX_LE                 0x40
@@ -457,7 +467,7 @@
 #define BCSR3 0xFA400003
 
 #define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
-#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
 #define BCSR0_LED5		0x04	/* LED5 control 0='on' 1='off' */
 #define BCSR0_LED4		0x08	/* LED4 control 0='on' 1='off' */
 #define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */