X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8544DS.h;h=b650874225425733a14d7f78e9b9565a42288630;hb=df4a0796e86662536df2387ddcf969c2a704bcc2;hp=aeac35a84d1ea80976d4ccd3aef943437ba6c554;hpb=50c03c8cf494d91cdec39670d95337c743e16ec9;p=oweals%2Fu-boot.git diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index aeac35a84d..b650874225 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -40,18 +40,12 @@ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ + +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_DLL -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ - -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_DDR_ECC_CMD #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ /* @@ -61,8 +55,6 @@ */ #define CONFIG_ASSUME_AMD_FLASH -#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ - #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif @@ -74,19 +66,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ - -#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 -#define CFG_ALT_MEMTEST #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* @@ -95,6 +82,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) @@ -102,17 +90,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) -/* - * DDR Setup - */ -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD + +#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CFG_DDR_SDRAM_BASE 0x00000000 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -/* - * Make sure required options are set - */ +/* Make sure required options are set */ #ifndef CONFIG_SPD_EEPROM #error ("CONFIG_SPD_EEPROM is required") #endif @@ -149,8 +147,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ -#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ - #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ #define CFG_BR0_PRELIM 0xff801001 @@ -159,17 +155,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_OR0_PRELIM 0xff806e65 #define CFG_OR1_PRELIM 0xff806e65 -#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE} +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_FLASH_QUIET_TEST +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_EMPTY_INFO @@ -198,34 +196,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ +#define PIXIS_VSPEED2_TSEC1SER 0x2 +#define PIXIS_VSPEED2_TSEC3SER 0x1 +#define PIXIS_VCFGEN1_TSEC1SER 0x20 +#define PIXIS_VCFGEN1_TSEC3SER 0x40 /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM 1 -#define CFG_INIT_L1_LOCK 1 -#define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ -#define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */ - -/* define to use L2SRAM as initial stack */ -#undef CONFIG_L2_INIT_RAM -#define CFG_INIT_L2_ADDR 0xf8fc0000 -#define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */ - -#ifdef CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR -#define CFG_INIT_RAM_END CFG_INIT_L1_END -#else -#define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR -#define CFG_INIT_RAM_END CFG_INIT_L2_END -#endif +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ +#define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -255,6 +246,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CFG_64BIT_STRTOUL 1 +#define CFG_64BIT_VSPRINTF 1 + /* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -313,6 +307,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI) +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CFG_PCIE2_IO_PHYS + +/*PCI video card used*/ +/*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ + +/* video */ +#define CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_CONSOLE_CURSOR*/ +#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -360,6 +374,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1c + #define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1 @@ -377,14 +394,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Environment */ -#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH 1 #if CFG_MONITOR_BASE > 0xfff80000 -#define CFG_ENV_ADDR 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 #else -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) #endif -#define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -406,6 +423,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_ELF #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -442,13 +460,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions *