X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FMIP405.h;h=979495a72c2bfb9a6e66a5c393672daca9539f2e;hb=2399ef73859f7ef54d2da9c3274c01f86726eff8;hp=58764d0dfbd2b63c7342f9dfec1829ca2accdc7c;hpb=6d8d4ef994a7c46e34b5fe53b1af7aa4f78192bf;p=oweals%2Fu-boot.git

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 58764d0dfb..979495a72c 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -91,7 +91,6 @@
 
 
 #define	 CONFIG_SYS_HUSH_PARSER
-#define	 CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /**************************************************************
  * I2C Stuff:
  * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
@@ -239,11 +238,17 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
 
 /*
  * JFFS2 partitions
@@ -291,6 +296,7 @@
 #define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
 
 #define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_R
 
 /* Peripheral Bus Mapping */
 #define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
@@ -308,9 +314,8 @@
 #define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
-#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for POST and BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
 
@@ -335,7 +340,6 @@
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 #define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
 #define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this */
-#define CONFIG_NET_MULTI
 /************************************************************
  * RTC
  ***********************************************************/