X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FM5253DEMO.h;h=b5af493b804ee755c4b94966b7c48186d63708f4;hb=be1a91320ce0cb7330bb650d1576bb56c55092af;hp=3a5c12faa46f9988aeb24f47af989d502186191d;hpb=50bd0057ba8fceeb48533f8b1a652ccd0e170838;p=oweals%2Fu-boot.git

diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 3a5c12faa4..b5af493b80 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -57,6 +57,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
 #define CONFIG_CMD_EXT2
@@ -85,21 +86,16 @@
 #	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
 #	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
 #	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
-#	define _IO_BASE			0
 #endif
 
+#define CONFIG_NET_MULTI		1
 #define CONFIG_DRIVER_DM9000
 #ifdef CONFIG_DRIVER_DM9000
-#	define CONFIG_DM9000_BASE	((CONFIG_SYS_CSAR1 << 16) | 0x300)
+#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
 #	define DM9000_IO		CONFIG_DM9000_BASE
 #	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
 #	undef CONFIG_DM9000_DEBUG
 
-#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
-#	define CONFIG_IPADDR		10.82.121.249
-#	define CONFIG_NETMASK		255.255.252.0
-#	define CONFIG_SERVERIP		10.82.120.80
-#	define CONFIG_GATEWAYIP		10.82.123.254
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 
 #	define CONFIG_EXTRA_ENV_SETTINGS		\
@@ -109,9 +105,9 @@
 		"u-boot=u-boot.bin\0"			\
 		"load=tftp ${loadaddr) ${u-boot}\0"	\
 		"upd=run load; run prog\0"		\
-		"prog=prot off 0 2ffff;"	\
-		"era 0 2ffff;"			\
-		"cp.b ${loadaddr} 0 ${filesize};"	\
+		"prog=prot off 0xff800000 0xff82ffff;"	\
+		"era 0xff800000 0xff82ffff;"		\
+		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
 		"save\0"				\
 		""
 #endif
@@ -200,9 +196,10 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
 
 /* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	1000
@@ -230,24 +227,30 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(8) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
-#define CONFIG_SYS_CSAR0		0xFF80
-#define CONFIG_SYS_CSMR0		0x007F0021
-#define CONFIG_SYS_CSCR0		0x1D80
-
-#define CONFIG_SYS_CSAR1               0xE000
-#define CONFIG_SYS_CSMR1               0x00000001
-#define CONFIG_SYS_CSCR1               0x3DD8
-
-#define CONFIG_SYS_CSAR2		0
-#define CONFIG_SYS_CSMR2		0
-#define CONFIG_SYS_CSCR2		0
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		0x007F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
 
-#define CONFIG_SYS_CSAR3		0
-#define CONFIG_SYS_CSMR3		0
-#define CONFIG_SYS_CSCR3		0
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		0x00000001
+#define CONFIG_SYS_CS1_CTRL		0x00003DD8
 
 /*-----------------------------------------------------------------------
  * Port configuration