X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FGEN860T.h;h=51cf5794b9af66f62d2e6f0aa311804d965598a2;hb=bb1f8b4f8bb0bfce52e0faa4637b975b745824b3;hp=29e4807ea2ae63227c062baa2d3164c2a9e0e8b2;hpb=5b1d713721c3ea02549940133f09236783dda1f9;p=oweals%2Fu-boot.git diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 29e4807ea2..51cf5794b9 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -38,30 +38,38 @@ /* * Identify the board */ -#define CONFIG_IDENT_STRING " GEN860T" +#if !defined(CONFIG_SC) +#define CONFIG_IDENT_STRING " B2" +#else +#define CONFIG_IDENT_STRING " SC" +#endif /* * Don't depend on the RTC clock to determine clock frequency - * the 860's internal rtc uses a 32.768 KHz clock which is * generated by the DS1337 - and the DS1337 clock can be turned off. */ -#define CONFIG_8xx_GCLK_FREQ 66600000 +#if !defined(CONFIG_SC) +#define CONFIG_8xx_GCLK_FREQ 66600000 +#else +#define CONFIG_8xx_GCLK_FREQ 48000000 +#endif /* * The RS-232 console port is on SMC1 */ #define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 /* * Set allowable console baud rates */ -#define CFG_BAUDRATE_TABLE { 9600, \ - 19200, \ - 38400, \ - 57600, \ - 115200, \ - } +#define CFG_BAUDRATE_TABLE { 9600, \ + 19200, \ + 38400, \ + 57600, \ + 115200, \ + } /* * Print console information @@ -84,8 +92,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* @@ -124,9 +132,12 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE \ - ) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * The GEN860T network interface uses the on-chip 10/100 FEC with @@ -136,14 +147,15 @@ #define CONFIG_FEC_ENET #define CFG_DISCOVER_PHY #define CONFIG_MII -#define CONFIG_PHY_ADDR 0 +#define CONFIG_MII_INIT 1 +#define CONFIG_PHY_ADDR 0 /* * Set default IP stuff just to get bootstrap entries into the * environment so that we can autoscript the full default environment. */ #define CONFIG_ETHADDR 9a:52:63:15:85:25 -#define CONFIG_SERVERIP 10.0.4.200 +#define CONFIG_SERVERIP 10.0.4.201 #define CONFIG_IPADDR 10.0.4.111 /* @@ -156,17 +168,20 @@ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ #define CFG_ENV_EEPROM_SIZE (32 * 1024) -#undef CONFIG_HARD_I2C -#define CONFIG_SOFT_I2C - /* - * Configure software I2C support (taken from IP860 BSP). - * The I2C bus is connected to the GEN860T's 'dedicated' I2C - * pins, i.e. PB26 and PB27 + * Enable I2C and select the hardware/software driver */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ +#define CONFIG_HARD_I2C 1 /* CPM based I2C */ +#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ + +#ifdef CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100000 /* clock speed in Hz */ +#define CFG_I2C_SLAVE 0xFE /* I2C slave address */ +#endif +#ifdef CONFIG_SOFT_I2C +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) @@ -176,15 +191,14 @@ #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ else immr->im_cpm.cp_pbdat &= ~PB_SCL #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 100000 /* clock speed in Hz */ -#define CFG_I2C_SLAVE 0xFE /* I2C slave address */ +#endif /* * Allow environment overwrites by anyone */ #define CONFIG_ENV_OVERWRITE +#if !defined(CONFIG_SC) /* * The MPC860's internal RTC is horribly broken in rev D masks. Three * internal MPC860T circuit nodes were inadvertently left floating; this @@ -193,35 +207,50 @@ * reasonable battery can keep that kind RTC running during powerdown for any * length of time, so we use an external RTC on the I2C bus instead. */ -#undef CONFIG_RTC_MPC8xx #define CONFIG_RTC_DS1337 #define CFG_I2C_RTC_ADDR 0x68 +#else /* - * Allow partial commands to be matched to uniqueness. + * No external RTC on SC variant, so we're stuck with the internal one. */ -#define CFG_MATCH_PARTIAL_CMD +#define CONFIG_RTC_MPC8xx +#endif /* - * List of available monitor commands. Use the system default list - * plus add some of the "non-standard" commands back in. - * See ./cmd_confdefs.h + * Power On Self Test support */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_DATE | \ - CFG_CMD_FPGA | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) +#define CONFIG_POST ( CFG_POST_CACHE | \ + CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_SPR ) + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_MII +#define CONFIG_CMD_BEDBUG + +#if !defined(CONFIG_SC) + #define CONFIG_CMD_DOC +#endif + +#ifdef CONFIG_POST +#define CONFIG_CMD_DIAG +#endif /* * There is no IDE/PCMCIA hardware support on the board. @@ -245,20 +274,24 @@ * Virtex2 FPGA configuration support */ #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA CFG_XILINX_VIRTEX2 +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_VIRTEX2 #define CFG_FPGA_PROG_FEEDBACK -/************************************************************************ - * This must be included AFTER the definition of any CONFIG_COMMANDS - */ -#include +#define CONFIG_NAND_LEGACY /* * Verbose help from command monitor. */ #define CFG_LONGHELP -#define CFG_PROMPT "gen860t> " +#if !defined(CONFIG_SC) +#define CFG_PROMPT "B2> " +#else +#define CFG_PROMPT "SC> " +#endif + /* * Use the "hush" command parser @@ -269,7 +302,7 @@ /* * Set buffer size for console I/O */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 #else #define CFG_CBSIZE 256 @@ -355,7 +388,7 @@ */ #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ +#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -393,29 +426,29 @@ /* * Reserve memory for U-Boot. */ -#define CFG_MAX_U_BOOT_SECT 3 - -#if defined(DEBUG) -#define CFG_MONITOR_LEN (512 * 1024) -#else -#define CFG_MONITOR_LEN (256 * 1024) -#endif - -#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MAX_UBOOT_SECTS 4 +#define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE) +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* * Select environment placement. NOTE that u-boot.lds must * be edited if this is changed! */ #undef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_IS_IN_EEPROM -#if defined(CFG_ENV_IS_IN_EEPROM) +#if defined(CONFIG_ENV_IS_IN_EEPROM) #define CFG_ENV_SIZE (2 * 1024) #define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024)) #else -#define CFG_ENV_SIZE (4 * 1024) -#define CFG_ENV_OFFSET (CFG_MAX_U_BOOT_SECT * CFG_FLASH_SECT_SIZE) +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE + +/* + * This ultimately gets passed right into the linker script, so we have to + * use a number :( + */ +#define CFG_ENV_OFFSET 0x060000 #endif /* @@ -434,12 +467,12 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */ #endif /*------------------------------------------------------------------------ - * SYPCR - System Protection Control UM 11-9 + * SYPCR - System Protection Control UM 11-9 * ----------------------------------------------------------------------- * SYPCR can only be written once after reset! * @@ -447,18 +480,18 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ + SYPCR_SWE | \ SYPCR_SWRI | \ SYPCR_SWP \ ) #else #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ SYPCR_SWP \ ) #endif @@ -523,13 +556,25 @@ */ #define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ +#if !defined(CONFIG_SC) +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ SCCR_DFNL000 | \ SCCR_DFNH000 \ ) +#else +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ + SCCR_DFNL000 | \ + SCCR_DFNH000 | \ + SCCR_RTDIV | \ + SCCR_RTSEL \ + ) +#endif /*----------------------------------------------------------------------- * DER - Debug Enable Register UM 37-46 @@ -569,7 +614,7 @@ #define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ BR_MS_GPCM | \ BR_PS_8 | \ - BR_V \ + BR_V \ ) /* @@ -581,9 +626,9 @@ ) #define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ + BR_MS_UPMA | \ + BR_PS_32 | \ + BR_V \ ) /* @@ -601,9 +646,9 @@ * MAMR settings for SDRAM */ #define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ + MAMR_PTAE | \ MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ + MAMR_DSA_1_CYCL | \ MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | \ MAMR_WLFA_1X | \ @@ -615,7 +660,7 @@ * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, * no burst. */ -#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_CSNT_SAM | \ OR_ACS_DIV2 | \ OR_BI | \ @@ -640,20 +685,20 @@ */ #define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ OR_SCY_15_CLK | \ - OR_BI \ + OR_BI \ ) #define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ BR_PS_32 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* * CS4* configuration for FPGA SelectMap configuration interface. * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge * of GCLK1_50 */ -#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_G5LS | \ OR_BI \ ) @@ -661,7 +706,7 @@ #define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ BR_PS_8 | \ BR_MS_UPMB | \ - BR_V \ + BR_V \ ) /* @@ -683,7 +728,7 @@ #define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ BR_PS_16 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* @@ -695,10 +740,12 @@ /* * Disk On Chip (millenium) configuration */ +#if !defined(CONFIG_SC) #define CFG_MAX_DOC_DEVICE 1 #undef CFG_DOC_SUPPORT_2000 #define CFG_DOC_SUPPORT_MILLENNIUM #undef CFG_DOC_PASSIVE_PROBE +#endif /* * FEC interrupt assignment @@ -713,5 +760,3 @@ #endif #endif /* __CONFIG_GEN860T_H */ - -/* vim: set ts=4 tw=78 ai shiftwidth=4: */