X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FCATcenter.h;h=1603c9c0bdada1f4a7865f1f57226906681690cd;hb=a55d074dac24dc941f1afb5b4e94b1509bfdda4e;hp=61022e8d5ba3bdb0334a29a6fd773625c75cdc45;hpb=3c71f3e8aa4d74bc5b43dc55f9be893afbc13497;p=oweals%2Fu-boot.git diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 61022e8d5b..1603c9c0bd 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -119,24 +119,36 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -155,7 +167,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -193,6 +205,8 @@ */ #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define NAND_BIG_DELAY_US 25 /* For CATcenter there is only NAND on the module */ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ @@ -218,9 +232,9 @@ #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define NAND_DISABLE_CE(nand) do \ +#define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ @@ -231,9 +245,9 @@ } \ } while(0) -#define NAND_ENABLE_CE(nand) do \ +#define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ @@ -244,8 +258,7 @@ } \ } while(0) - -#define NAND_CTL_CLRALE(nandptr) do \ +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -258,7 +271,7 @@ } \ } while(0) -#define NAND_CTL_SETALE(nandptr) do \ +#define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -271,7 +284,7 @@ } \ } while(0) -#define NAND_CTL_CLRCLE(nandptr) do \ +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -284,7 +297,7 @@ } \ } while(0) -#define NAND_CTL_SETCLE(nandptr) do { \ +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ @@ -377,11 +390,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Environment Variable setup */ @@ -391,6 +399,8 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */ @@ -414,10 +424,10 @@ /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -463,7 +473,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/videomodes.c */ +/* see also drivers/video/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif @@ -767,9 +777,26 @@ #endif /* CONFIG_NO_SERIAL_EEPROM */ #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ -#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ -#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand" +#define CONFIG_JFFS2_PART_SIZE 0x00200000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support + * + * Note: fake mtd_id used, no linux mtd map file + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=catcenter" +#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)" +*/ + #endif /* __CONFIG_H */