X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fconfigs%2FAPC405.h;h=9a65cbced094cf9cd8a9da7af0767caef90668d1;hb=a51425d2a4e51381423bff9329042e66fedb7cb6;hp=a7724adb42c41bc3515d03c8532baecb23ee1cff;hpb=38570b2ff3b618892b7b7f2d4c80f5b79d49018f;p=oweals%2Fu-boot.git

diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index a7724adb42..9a65cbced0 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -38,6 +38,8 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_APCG405		1	/* ...on a APC405 board		*/
 
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_BOARD_EARLY_INIT_R 1
 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
@@ -101,7 +103,6 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
 #define CONFIG_PPC4xx_EMAC
@@ -176,6 +177,12 @@
 #define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
 #define CONFIG_SYS_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
 
 /* The following table includes the supported baudrates */
@@ -264,16 +271,10 @@
 /*
  * FLASH organization
  */
-#ifndef __ASSEMBLY__
-extern int flash_banks;
-#endif
-
 #define CONFIG_SYS_FLASH_BASE		0xFE000000
 #define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	flash_banks /* max num of flash banks */
-					    /* updated in board_early_init_r */
 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
 #define CONFIG_SYS_FLASH_QUIET_TEST	1
 #define CONFIG_SYS_FLASH_INCREMENT	0x01000000
@@ -418,9 +419,8 @@ extern int flash_banks;
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* reserved bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
 
@@ -428,14 +428,6 @@ extern int flash_banks;
 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
 #endif
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
 /*
  * PCI OHCI controller
  */