X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-ppc%2Ffsl_lbc.h;h=5723de643a483e4fc06292ff8ea5a8f337893ad1;hb=2ff6922280025c1315c53fa2eb4ab33f0c9591de;hp=ea49ddc515d9eddb62804906fd24444e163c0f9a;hpb=ce0eb70333331da6942167c41e6841c8c7994a33;p=oweals%2Fu-boot.git diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index ea49ddc515..5723de643a 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -28,6 +28,8 @@ #define BR_BA 0xFFFF8000 #define BR_BA_SHIFT 15 +#define BR_XBA 0x00006000 +#define BR_XBA_SHIFT 13 #define BR_PS 0x00001800 #define BR_PS_SHIFT 11 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ @@ -52,7 +54,7 @@ #define BR_MS_UPMA 0x00000080 /* UPMA */ #define BR_MS_UPMB 0x000000A0 /* UPMB */ #define BR_MS_UPMC 0x000000C0 /* UPMC */ -#if !defined(CONFIG_MPC834X) +#if !defined(CONFIG_MPC834x) #define BR_ATOM 0x0000000C #define BR_ATOM_SHIFT 2 #endif @@ -63,12 +65,20 @@ #define UPMB 1 #define UPMC 2 -#if defined(CONFIG_MPC834X) +#if defined(CONFIG_MPC834x) #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) #else #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) #endif +/* Convert an address into the right format for the BR registers */ +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) +#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ + ((x & 0x300000000ULL) >> 19))) +#else +#define BR_PHYS_ADDR(x) (x & 0xffff8000) +#endif + /* OR - Option Registers */ #define OR0 0x5004 /* Register offset to immr */ @@ -82,6 +92,8 @@ #define OR_GPCM_AM 0xFFFF8000 #define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_XAM 0x00006000 +#define OR_GPCM_XAM_SHIFT 13 #define OR_GPCM_BCTLD 0x00001000 #define OR_GPCM_BCTLD_SHIFT 12 #define OR_GPCM_CSNT 0x00000800 @@ -124,6 +136,8 @@ #define OR_FCM_AM 0xFFFF8000 #define OR_FCM_AM_SHIFT 15 +#define OR_FCM_XAM 0x00006000 +#define OR_FCM_XAM_SHIFT 13 #define OR_FCM_BCTLD 0x00001000 #define OR_FCM_BCTLD_SHIFT 12 #define OR_FCM_PGS 0x00000400 @@ -292,11 +306,26 @@ #define LCRR_EADC_2 0x00020000 #define LCRR_EADC_3 0x00030000 #define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F +/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit + * should always be zero on older parts that have a four bit CLKDIV. + */ +#define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 +#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ + defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ + defined(CONFIG_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#elif defined(CONFIG_FSL_CORENET) +#define LCRR_CLKDIV_8 0x00000002 +#define LCRR_CLKDIV_16 0x00000004 +#define LCRR_CLKDIV_32 0x00000008 +#else +#define LCRR_CLKDIV_4 0x00000002 +#define LCRR_CLKDIV_8 0x00000004 +#define LCRR_CLKDIV_16 0x00000008 +#endif /* LTEDR - Transfer Error Check Disable Register */ @@ -307,4 +336,161 @@ #define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */ #define LTEDR_CSD 0x00080000 /* Chip select error checking disable */ +/* FMR - Flash Mode Register + */ +#define FMR_CWTO 0x0000F000 +#define FMR_CWTO_SHIFT 12 +#define FMR_BOOT 0x00000800 +#define FMR_ECCM 0x00000100 +#define FMR_AL 0x00000030 +#define FMR_AL_SHIFT 4 +#define FMR_OP 0x00000003 +#define FMR_OP_SHIFT 0 + +/* FIR - Flash Instruction Register + */ +#define FIR_OP0 0xF0000000 +#define FIR_OP0_SHIFT 28 +#define FIR_OP1 0x0F000000 +#define FIR_OP1_SHIFT 24 +#define FIR_OP2 0x00F00000 +#define FIR_OP2_SHIFT 20 +#define FIR_OP3 0x000F0000 +#define FIR_OP3_SHIFT 16 +#define FIR_OP4 0x0000F000 +#define FIR_OP4_SHIFT 12 +#define FIR_OP5 0x00000F00 +#define FIR_OP5_SHIFT 8 +#define FIR_OP6 0x000000F0 +#define FIR_OP6_SHIFT 4 +#define FIR_OP7 0x0000000F +#define FIR_OP7_SHIFT 0 +#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ +#define FIR_OP_CA 0x1 /* Issue current column address */ +#define FIR_OP_PA 0x2 /* Issue current block+page address */ +#define FIR_OP_UA 0x3 /* Issue user defined address */ +#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ +#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ +#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ +#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ +#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ +#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ +#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ +#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ +#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ +#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ +#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ +#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ + +/* FCR - Flash Command Register + */ +#define FCR_CMD0 0xFF000000 +#define FCR_CMD0_SHIFT 24 +#define FCR_CMD1 0x00FF0000 +#define FCR_CMD1_SHIFT 16 +#define FCR_CMD2 0x0000FF00 +#define FCR_CMD2_SHIFT 8 +#define FCR_CMD3 0x000000FF +#define FCR_CMD3_SHIFT 0 +/* FBAR - Flash Block Address Register + */ +#define FBAR_BLK 0x00FFFFFF + +/* FPAR - Flash Page Address Register + */ +#define FPAR_SP_PI 0x00007C00 +#define FPAR_SP_PI_SHIFT 10 +#define FPAR_SP_MS 0x00000200 +#define FPAR_SP_CI 0x000001FF +#define FPAR_SP_CI_SHIFT 0 +#define FPAR_LP_PI 0x0003F000 +#define FPAR_LP_PI_SHIFT 12 +#define FPAR_LP_MS 0x00000800 +#define FPAR_LP_CI 0x000007FF +#define FPAR_LP_CI_SHIFT 0 + +/* LSDMR - SDRAM Machine Mode Register + */ +#define LSDMR_RFEN (1 << (31 - 1)) +#define LSDMR_BSMA1516 (3 << (31 - 10)) +#define LSDMR_BSMA1617 (4 << (31 - 10)) +#define LSDMR_RFCR5 (3 << (31 - 16)) +#define LSDMR_RFCR16 (7 << (31 - 16)) +#define LSDMR_PRETOACT3 (3 << (31 - 19)) +#define LSDMR_PRETOACT7 (7 << (31 - 19)) +#define LSDMR_ACTTORW3 (3 << (31 - 22)) +#define LSDMR_ACTTORW7 (7 << (31 - 22)) +#define LSDMR_ACTTORW6 (6 << (31 - 22)) +#define LSDMR_BL8 (1 << (31 - 23)) +#define LSDMR_WRC2 (2 << (31 - 27)) +#define LSDMR_WRC4 (0 << (31 - 27)) +#define LSDMR_BUFCMD (1 << (31 - 29)) +#define LSDMR_CL3 (3 << (31 - 31)) + +#define LSDMR_OP_NORMAL (0 << (31 - 4)) +#define LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define LSDMR_OP_MRW (3 << (31 - 4)) +#define LSDMR_OP_PRECH (4 << (31 - 4)) +#define LSDMR_OP_PCHALL (5 << (31 - 4)) +#define LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define LSDMR_OP_RWINV (7 << (31 - 4)) + +/* LTESR - Transfer Error Status Register + */ +#define LTESR_BM 0x80000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 +#define LTESR_WP 0x04000000 +#define LTESR_ATMW 0x00800000 +#define LTESR_ATMR 0x00400000 +#define LTESR_CS 0x00080000 +#define LTESR_CC 0x00000001 + +#ifndef __ASSEMBLY__ +/* + * Local Bus Controller Registers. + */ +typedef struct lbus_bank { + u32 br; /* Base Register */ + u32 or; /* Option Register */ +} lbus_bank_t; + +typedef struct fsl_lbus { + lbus_bank_t bank[8]; + u8 res0[0x28]; + u32 mar; /* UPM Address Register */ + u8 res1[0x4]; + u32 mamr; /* UPMA Mode Register */ + u32 mbmr; /* UPMB Mode Register */ + u32 mcmr; /* UPMC Mode Register */ + u8 res2[0x8]; + u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ + u32 mdr; /* UPM Data Register */ + u8 res3[0x4]; + u32 lsor; /* Special Operation Initiation Register */ + u32 lsdmr; /* SDRAM Mode Register */ + u8 res4[0x8]; + u32 lurt; /* UPM Refresh Timer */ + u32 lsrt; /* SDRAM Refresh Timer */ + u8 res5[0x8]; + u32 ltesr; /* Transfer Error Status Register */ + u32 ltedr; /* Transfer Error Disable Register */ + u32 lteir; /* Transfer Error Interrupt Register */ + u32 lteatr; /* Transfer Error Attributes Register */ + u32 ltear; /* Transfer Error Address Register */ + u8 res6[0xC]; + u32 lbcr; /* Configuration Register */ + u32 lcrr; /* Clock Ratio Register */ + u8 res7[0x8]; + u32 fmr; /* Flash Mode Register */ + u32 fir; /* Flash Instruction Register */ + u32 fcr; /* Flash Command Register */ + u32 fbar; /* Flash Block Addr Register */ + u32 fpar; /* Flash Page Addr Register */ + u32 fbcr; /* Flash Byte Count Register */ + u8 res8[0xF08]; +} fsl_lbus_t; +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_PPC_FSL_LBC_H */