X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-ppc%2Ffsl_ddr_sdram.h;h=c1ea7cd6bb16a3ff3ec68fa951e28f04dee6fbd5;hb=50bd0057ba8fceeb48533f8b1a652ccd0e170838;hp=8adde34247bd1364c6bfd419206e6895bf5ef438;hpb=58e5e9aff147e8c7e2bc1406bf9384f65f020ffa;p=oweals%2Fu-boot.git

diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 8adde34247..c1ea7cd6bb 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -36,6 +36,18 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #endif
 
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1			0x40
+#define FSL_DDR_CS2_CS3			0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
+#define FSL_DDR_PAGE_INTERLEAVING	0x1
+#define FSL_DDR_BANK_INTERLEAVING	0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
 	struct {