X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-ppc%2F4xx_pcie.h;h=a0e88de11d4390bb38b2b2fb06f81ada33804223;hb=26f6a2b7f3d215a0bd291e8b37be5a359878037c;hp=d27d2a965ce7da89ef1fa39d9eebb92d830207fd;hpb=27f33e9f45ef7f9685cbdc65066a1828e85dde4f;p=oweals%2Fu-boot.git diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index d27d2a965c..a0e88de11d 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -8,17 +8,19 @@ * option) any later version. */ -#include #ifndef __4XX_PCIE_H #define __4XX_PCIE_H +#include +#include + #define DCRN_SDR0_CFGADDR 0x00e #define DCRN_SDR0_CFGDATA 0x00f #if defined(CONFIG_440SPE) -#define CFG_PCIE_NR_PORTS 3 +#define CONFIG_SYS_PCIE_NR_PORTS 3 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -30,9 +32,9 @@ #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -42,9 +44,9 @@ #endif #if defined(CONFIG_405EX) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x00000000 +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000 #define DCRN_PCIE0_BASE 0x040 #define DCRN_PCIE1_BASE 0x060 @@ -395,6 +397,7 @@ static inline void mdelay(int n) udelay(1000); } +#if defined(PCIE0_SDR) static inline u32 sdr_base(int port) { switch (port) { @@ -403,11 +406,12 @@ static inline u32 sdr_base(int port) return PCIE0_SDR; case 1: return PCIE1_SDR; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: return PCIE2_SDR; #endif } } +#endif /* defined(PCIE0_SDR) */ #endif /* __4XX_PCIE_H */