X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-ppc%2F4xx_pcie.h;h=a0e88de11d4390bb38b2b2fb06f81ada33804223;hb=26f6a2b7f3d215a0bd291e8b37be5a359878037c;hp=38745eb797cdafa230c93cedd32db04bd12fa21a;hpb=c7c6da23028f146d912514b95aefa3da7cf37699;p=oweals%2Fu-boot.git diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index 38745eb797..a0e88de11d 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -8,18 +8,53 @@ * option) any later version. */ -#include -#ifndef __440SPE_PCIE_H -#define __440SPE_PCIE_H +#ifndef __4XX_PCIE_H +#define __4XX_PCIE_H -#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) +#include +#include #define DCRN_SDR0_CFGADDR 0x00e #define DCRN_SDR0_CFGDATA 0x00f +#if defined(CONFIG_440SPE) +#define CONFIG_SYS_PCIE_NR_PORTS 3 + +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d + #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 #define DCRN_PCIE2_BASE 0x140 + +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#define PCIE2_SDR 0x370 +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define CONFIG_SYS_PCIE_NR_PORTS 2 + +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 + +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#endif + +#if defined(CONFIG_405EX) +#define CONFIG_SYS_PCIE_NR_PORTS 2 + +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000 + +#define DCRN_PCIE0_BASE 0x040 +#define DCRN_PCIE1_BASE 0x060 + +#define PCIE0_SDR 0x400 +#define PCIE1_SDR 0x440 +#endif + #define PCIE0 DCRN_PCIE0_BASE #define PCIE1 DCRN_PCIE1_BASE #define PCIE2 DCRN_PCIE2_BASE @@ -47,6 +82,28 @@ #define PESDR0_PLLLCT2 0x03a1 #define PESDR0_PLLLCT3 0x03a2 +/* common regs, at for all 4xx with PCIe core */ +#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) +#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) +#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02) +#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03) +#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04) +#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05) + +#if defined(CONFIG_440SPE) +#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09) +#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a) +#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c) +#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d) +#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e) +#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f) +#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10) +#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11) + #define PESDR0_UTLSET1 0x0300 #define PESDR0_UTLSET2 0x0301 #define PESDR0_DLPSET 0x0302 @@ -123,9 +180,109 @@ #define PESDR2_HSSCTLSET 0x0382 #define PESDR2_LANE_ABCD 0x0383 +#elif defined(CONFIG_405EX) + +#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c) + +#define PESDR0_UTLSET1 0x0400 +#define PESDR0_UTLSET2 0x0401 +#define PESDR0_DLPSET 0x0402 +#define PESDR0_LOOP 0x0403 +#define PESDR0_RCSSET 0x0404 +#define PESDR0_RCSSTS 0x0405 +#define PESDR0_PHYSET1 0x0406 +#define PESDR0_PHYSET2 0x0407 +#define PESDR0_BIST 0x0408 +#define PESDR0_LPB 0x040B +#define PESDR0_PHYSTA 0x040C + +#define PESDR1_UTLSET1 0x0440 +#define PESDR1_UTLSET2 0x0441 +#define PESDR1_DLPSET 0x0442 +#define PESDR1_LOOP 0x0443 +#define PESDR1_RCSSET 0x0444 +#define PESDR1_RCSSTS 0x0445 +#define PESDR1_PHYSET1 0x0446 +#define PESDR1_PHYSET2 0x0447 +#define PESDR1_BIST 0x0448 +#define PESDR1_LPB 0x044B +#define PESDR1_PHYSTA 0x044C + +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) + +#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */ +#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */ +#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */ +#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */ +#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */ +#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */ +#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */ +#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */ +#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */ +#define PESDR0_OBS 0x0311 /* PE0 observation register */ +#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */ + +#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */ +#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */ +#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */ +#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */ +#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */ +#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */ +#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */ +#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */ +#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */ +#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */ +#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */ +#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */ +#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */ +#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */ +#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */ +#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */ +#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */ +#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */ +#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */ +#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */ +#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */ +#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */ +#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */ +#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */ +#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */ +#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */ +#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */ +#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */ +#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */ +#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */ +#define PESDR1_OBS 0x0366 /* PE1 observation register */ +#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */ +#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */ +#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */ +#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */ +#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */ +#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */ + +#endif + +/* SDR Bit Mappings */ +#define PESDRx_RCSSET_HLDPLB 0x10000000 +#define PESDRx_RCSSET_RSTGU 0x01000000 +#define PESDRx_RCSSET_RDY 0x00100000 +#define PESDRx_RCSSET_RSTDL 0x00010000 +#define PESDRx_RCSSET_RSTPYN 0x00001000 + +#define PESDRx_RCSSTS_PLBIDL 0x10000000 +#define PESDRx_RCSSTS_HRSTRQ 0x01000000 +#define PESDRx_RCSSTS_PGRST 0x00100000 +#define PESDRx_RCSSTS_VC0ACT 0x00010000 +#define PESDRx_RCSSTS_BMEN 0x00000100 + /* * UTL register offsets */ +#define PEUTL_PBCTL 0x00 #define PEUTL_PBBSZ 0x20 #define PEUTL_OPDBSZ 0x68 #define PEUTL_IPHBSZ 0x70 @@ -133,6 +290,7 @@ #define PEUTL_OUTTR 0x90 #define PEUTL_INTR 0x98 #define PEUTL_PCTL 0xa0 +#define PEUTL_RCSTA 0xb0 #define PEUTL_RCIRQEN 0xb8 /* @@ -141,7 +299,8 @@ #define PECFG_BAR0LMPA 0x210 #define PECFG_BAR0HMPA 0x214 #define PECFG_BAR1MPA 0x218 -#define PECFG_BAR2MPA 0x220 +#define PECFG_BAR2LMPA 0x220 +#define PECFG_BAR2HMPA 0x224 #define PECFG_PIMEN 0x33c #define PECFG_PIM0LAL 0x340 @@ -164,11 +323,95 @@ #define GPL_DMER_MASK_DISA 0x02000000 -int ppc440spe_init_pcie(void); -int ppc440spe_init_pcie_rootport(int port); -void yucca_setup_pcie_fpga_rootpoint(int port); -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); -int yucca_pcie_card_present(int port); +#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) +#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) + +/* + * Prototypes + */ +int ppc4xx_init_pcie(void); +int ppc4xx_init_pcie_rootport(int port); +int ppc4xx_init_pcie_endport(int port); +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); -#endif /* __440SPE_PCIE_H */ + +/* + * Function to determine root port or endport from env variable. + */ +static inline int is_end_point(int port) +{ + char s[10], *tk; + char *pcie_mode = getenv("pcie_mode"); + + if (pcie_mode == NULL) + return 0; + + strcpy(s, pcie_mode); + tk = strtok(s, ":"); + + switch (port) { + case 0: + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 1: + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 2: + tk = strtok(NULL, ":"); + if (tk != NULL) + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + } + + return 0; +} + +static inline void mdelay(int n) +{ + u32 ms = n; + + while (ms--) + udelay(1000); +} + +#if defined(PCIE0_SDR) +static inline u32 sdr_base(int port) +{ + switch (port) { + default: /* to satisfy compiler */ + case 0: + return PCIE0_SDR; + case 1: + return PCIE1_SDR; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + return PCIE2_SDR; +#endif + } +} +#endif /* defined(PCIE0_SDR) */ + +#endif /* __4XX_PCIE_H */