X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-ppc%2F4xx_pcie.h;h=4c03b050fef28d689f8fe4089cd983d76e8e2fb2;hb=f58934551e052db5a1f33f53dcc9cbf6fcb72910;hp=220c60cd761401fa3c4e64908bbd560304f0c95e;hpb=026f71106871f31d17d0ea0db9a7547ff92934bc;p=oweals%2Fu-boot.git

diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h
index 220c60cd76..4c03b050fe 100644
--- a/include/asm-ppc/4xx_pcie.h
+++ b/include/asm-ppc/4xx_pcie.h
@@ -12,14 +12,35 @@
 #ifndef __4XX_PCIE_H
 #define __4XX_PCIE_H
 
-#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);})
-
 #define DCRN_SDR0_CFGADDR	0x00e
 #define DCRN_SDR0_CFGDATA	0x00f
 
+#if defined(CONFIG_440SPE)
+#define CFG_PCIE_NR_PORTS	3
+
+#define CFG_PCIE_ADDR_HIGH	0x0000000d
+
 #define DCRN_PCIE0_BASE		0x100
 #define DCRN_PCIE1_BASE		0x120
 #define DCRN_PCIE2_BASE		0x140
+
+#define PCIE0_SDR		0x300
+#define PCIE1_SDR		0x340
+#define PCIE2_SDR		0x370
+#endif
+
+#if defined(CONFIG_405EX)
+#define CFG_PCIE_NR_PORTS	2
+
+#define CFG_PCIE_ADDR_HIGH	0x00000000
+
+#define	DCRN_PCIE0_BASE		0x040
+#define	DCRN_PCIE1_BASE		0x060
+
+#define PCIE0_SDR		0x400
+#define PCIE1_SDR		0x440
+#endif
+
 #define PCIE0			DCRN_PCIE0_BASE
 #define PCIE1			DCRN_PCIE1_BASE
 #define PCIE2			DCRN_PCIE2_BASE
@@ -47,6 +68,28 @@
 #define PESDR0_PLLLCT2		0x03a1
 #define PESDR0_PLLLCT3		0x03a2
 
+/* common regs, at least for 405EX and 440SPe */
+#define SDRN_PESDR_UTLSET1(n)		(sdr_base(n) + 0x00)
+#define SDRN_PESDR_UTLSET2(n)		(sdr_base(n) + 0x01)
+#define SDRN_PESDR_DLPSET(n)		(sdr_base(n) + 0x02)
+#define SDRN_PESDR_LOOP(n)		(sdr_base(n) + 0x03)
+#define SDRN_PESDR_RCSSET(n)		(sdr_base(n) + 0x04)
+#define SDRN_PESDR_RCSSTS(n)		(sdr_base(n) + 0x05)
+
+#if defined(CONFIG_440SPE)
+#define SDRN_PESDR_HSSL0SET1(n)		(sdr_base(n) + 0x06)
+#define SDRN_PESDR_HSSL0SET2(n)		(sdr_base(n) + 0x07)
+#define SDRN_PESDR_HSSL0STS(n)		(sdr_base(n) + 0x08)
+#define SDRN_PESDR_HSSL1SET1(n)		(sdr_base(n) + 0x09)
+#define SDRN_PESDR_HSSL1SET2(n)		(sdr_base(n) + 0x0a)
+#define SDRN_PESDR_HSSL1STS(n)		(sdr_base(n) + 0x0b)
+#define SDRN_PESDR_HSSL2SET1(n)		(sdr_base(n) + 0x0c)
+#define SDRN_PESDR_HSSL2SET2(n)		(sdr_base(n) + 0x0d)
+#define SDRN_PESDR_HSSL2STS(n)		(sdr_base(n) + 0x0e)
+#define SDRN_PESDR_HSSL3SET1(n)		(sdr_base(n) + 0x0f)
+#define SDRN_PESDR_HSSL3SET2(n)		(sdr_base(n) + 0x10)
+#define SDRN_PESDR_HSSL3STS(n)		(sdr_base(n) + 0x11)
+
 #define PESDR0_UTLSET1		0x0300
 #define PESDR0_UTLSET2		0x0301
 #define PESDR0_DLPSET		0x0302
@@ -123,9 +166,44 @@
 #define PESDR2_HSSCTLSET	0x0382
 #define PESDR2_LANE_ABCD	0x0383
 
+#elif defined(CONFIG_405EX)
+
+#define SDRN_PESDR_PHYSET1(n)		(sdr_base(n) + 0x06)
+#define SDRN_PESDR_PHYSET2(n)		(sdr_base(n) + 0x07)
+#define SDRN_PESDR_BIST(n)		(sdr_base(n) + 0x08)
+#define SDRN_PESDR_LPB(n)		(sdr_base(n) + 0x0b)
+#define SDRN_PESDR_PHYSTA(n)		(sdr_base(n) + 0x0c)
+
+#define PESDR0_UTLSET1		0x0400
+#define PESDR0_UTLSET2		0x0401
+#define PESDR0_DLPSET		0x0402
+#define PESDR0_LOOP		0x0403
+#define PESDR0_RCSSET		0x0404
+#define PESDR0_RCSSTS		0x0405
+#define PESDR0_PHYSET1		0x0406
+#define PESDR0_PHYSET2		0x0407
+#define PESDR0_BIST		0x0408
+#define PESDR0_LPB		0x040B
+#define PESDR0_PHYSTA		0x040C
+
+#define PESDR1_UTLSET1		0x0440
+#define PESDR1_UTLSET2		0x0441
+#define PESDR1_DLPSET		0x0442
+#define PESDR1_LOOP		0x0443
+#define PESDR1_RCSSET		0x0444
+#define PESDR1_RCSSTS		0x0445
+#define PESDR1_PHYSET1		0x0446
+#define PESDR1_PHYSET2		0x0447
+#define PESDR1_BIST		0x0448
+#define PESDR1_LPB		0x044B
+#define PESDR1_PHYSTA		0x044C
+
+#endif
+
 /*
  * UTL register offsets
  */
+#define	PEUTL_PBCTL		0x00
 #define PEUTL_PBBSZ		0x20
 #define PEUTL_OPDBSZ		0x68
 #define PEUTL_IPHBSZ		0x70
@@ -133,6 +211,7 @@
 #define PEUTL_OUTTR		0x90
 #define PEUTL_INTR		0x98
 #define PEUTL_PCTL		0xa0
+#define	PEUTL_RCSTA		0xb0
 #define PEUTL_RCIRQEN		0xb8
 
 /*
@@ -141,7 +220,8 @@
 #define PECFG_BAR0LMPA		0x210
 #define PECFG_BAR0HMPA		0x214
 #define PECFG_BAR1MPA		0x218
-#define PECFG_BAR2MPA		0x220
+#define PECFG_BAR2LMPA		0x220
+#define PECFG_BAR2HMPA		0x224
 
 #define PECFG_PIMEN		0x33c
 #define PECFG_PIM0LAL		0x340
@@ -164,10 +244,93 @@
 
 #define GPL_DMER_MASK_DISA	0x02000000
 
+#define U64_TO_U32_LOW(val)	((u32)((val) & 0x00000000ffffffffULL))
+#define U64_TO_U32_HIGH(val)	((u32)((val) >> 32))
+
+/*
+ * Prototypes
+ */
 int ppc4xx_init_pcie(void);
 int ppc4xx_init_pcie_rootport(int port);
+int ppc4xx_init_pcie_endport(int port);
 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
 int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
 int pcie_hose_scan(struct pci_controller *hose, int bus);
 
+/*
+ * Function to determine root port or endport from env variable.
+ */
+static inline int is_end_point(int port)
+{
+	char s[10], *tk;
+	char *pcie_mode = getenv("pcie_mode");
+
+	if (pcie_mode == NULL)
+		return 0;
+
+	strcpy(s, pcie_mode);
+	tk = strtok(s, ":");
+
+	switch (port) {
+	case 0:
+		if (tk != NULL) {
+			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+				return 1;
+			else
+				return 0;
+		}
+		else
+			return 0;
+
+	case 1:
+		tk = strtok(NULL, ":");
+		if (tk != NULL) {
+			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+				return 1;
+			else
+				return 0;
+		}
+		else
+			return 0;
+
+	case 2:
+		tk = strtok(NULL, ":");
+		if (tk != NULL)
+			tk = strtok(NULL, ":");
+		if (tk != NULL) {
+			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
+				return 1;
+			else
+				return 0;
+		}
+		else
+			return 0;
+	}
+
+	return 0;
+}
+
+static inline void mdelay(int n)
+{
+	u32 ms = n;
+
+	while (ms--)
+		udelay(1000);
+}
+
+static inline u32 sdr_base(int port)
+{
+	switch (port) {
+	default:	/* to satisfy compiler */
+	case 0:
+		return PCIE0_SDR;
+	case 1:
+		return PCIE1_SDR;
+#if CFG_PCIE_NR_PORTS > 2
+	case 2:
+		return PCIE2_SDR;
+#endif
+	}
+}
+
 #endif /* __4XX_PCIE_H */