X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-mips%2Fau1x00.h;h=a4e9947d93b3e0619ce99c0d46dfb8b679718d95;hb=41ec8b1803804b7e0644d07af4977c339a575b80;hp=917fd83ae6243cf3701e2dfd0a87ef9cec6da749;hpb=42d1f0394bef0624fc9664714d54bb137931d6a6;p=oweals%2Fu-boot.git

diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 917fd83ae6..a4e9947d93 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -119,6 +119,11 @@ static __inline__ int au_ffs(int x)
 	return __ilog2(x & -x) + 1;
 }
 
+#define gpio_set(Value)      outl(Value, SYS_OUTPUTSET)
+#define gpio_clear(Value)    outl(Value, SYS_OUTPUTCLR)
+#define gpio_read()          inl(SYS_PINSTATERD)
+#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
+
 #endif /* !ASSEMBLY */
 
 #ifdef CONFIG_PM
@@ -128,7 +133,31 @@ static __inline__ int au_ffs(int x)
 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 #endif
 
+#define CP0_IWATCHLO		$18,1
+#define CP0_DEBUG		$23
+
 /* SDRAM Controller */
+#ifdef CONFIG_AU1550
+
+#define MEM_SDMODE0                0xB4000800
+#define MEM_SDMODE1                0xB4000808
+#define MEM_SDMODE2                0xB4000810
+
+#define MEM_SDADDR0                0xB4000820
+#define MEM_SDADDR1                0xB4000828
+#define MEM_SDADDR2                0xB4000830
+
+#define MEM_SDCONFIGA              0xB4000840
+#define MEM_SDCONFIGB              0xB4000848
+#define MEM_SDPRECMD               0xB40008c0
+#define MEM_SDAUTOREF              0xB40008c8
+
+#define MEM_SDWRMD0                0xB4000880
+#define MEM_SDWRMD1                0xB4000888
+#define MEM_SDWRMD2                0xB4000890
+
+#else /* CONFIG_AU1550 */
+
 #define MEM_SDMODE0                0xB4000000
 #define MEM_SDMODE1                0xB4000004
 #define MEM_SDMODE2                0xB4000008
@@ -145,6 +174,8 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000028
 #define MEM_SDWRMD2                0xB400002C
 
+#endif /* CONFIG_AU1550 */
+
 #define MEM_SDSLEEP                0xB4000030
 #define MEM_SDSMCKE                0xB4000034
 
@@ -471,6 +502,8 @@ static __inline__ int au_ffs(int x)
 #define AU1500_ETH0_BASE	  0xB1500000
 #define AU1500_ETH1_BASE	  0xB1510000
 #define AU1100_ETH0_BASE	  0xB0500000
+#define AU1550_ETH0_BASE	  0xB0500000
+#define AU1550_ETH1_BASE	  0xB0510000
 
 /* 4 byte offsets from AU1000_ETH_BASE */
 #define MAC_CONTROL                     0x0
@@ -520,6 +553,8 @@ static __inline__ int au_ffs(int x)
 #define AU1500_MAC0_ENABLE       0xB1520000
 #define AU1500_MAC1_ENABLE       0xB1520004
 #define AU1100_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC1_ENABLE       0xB0520004
 
 #define MAC_EN_CLOCK_ENABLE         (1<<0)
 #define MAC_EN_RESET0               (1<<1)
@@ -976,6 +1011,15 @@ static __inline__ int au_ffs(int x)
 #define AC97C_RS              (1<<1)
 #define AC97C_CE              (1<<0)
 
+#define DB1000_BCSR_ADDR 0xAE000000
+#define DB1550_BCSR_ADDR 0xAF000000
+
+#ifdef CONFIG_DBAU1550
+#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
+#else
+#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
+#endif
+
 #ifdef CONFIG_SOC_AU1500
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE           0xB4005000 /* virtual, kseg0 addr */