X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-blackfin%2Fcplb.h;h=cc21e93a18546e9793caf7a621e9a5df527c7b0d;hb=3ec53148eb68ddfb0c3311fb4c06cd2bd0ef3eeb;hp=7aa712fe0aefeba34840d11c13d10c3b433099b8;hpb=20c93959330aba8b5bbdbfde1ef319e99eba235d;p=oweals%2Fu-boot.git

diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index 7aa712fe0a..cc21e93a18 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -42,8 +42,8 @@
 #define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
 #define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
 #define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL
+#define CPLB_INOCACHE		CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
 
 /* Data Attibutes*/
 
@@ -73,9 +73,4 @@
 #define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 #endif
 
-#if defined(CONFIG_BF561)
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4)	/* SDRAM +L1 + ASYNC_Memory */
-#else
-#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2)	/* SDRAM + L1 + ASYNC_Memory */
-#endif
 #endif				/* _CPLB_H */