X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Fasm-arm%2Fio.h;h=fec3a7eace50ce220355e03bdd5629eed23be80a;hb=c50a6031670a90f799835db7bc1638a3e2a9f1f0;hp=029b7f9eeb41de1431927e00a26e2aea980e7eef;hpb=f77ac3d657e9b1d40012153e872a2118cca10a3d;p=oweals%2Fu-boot.git

diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 029b7f9eeb..fec3a7eace 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -38,8 +38,6 @@ static inline void sync(void)
  * that can be used to access the memory range with the caching
  * properties specified by "flags".
  */
-typedef unsigned long phys_addr_t;
-
 #define MAP_NOCACHE	(0)
 #define MAP_WRCOMBINE	(0)
 #define MAP_WRBACK	(0)
@@ -59,6 +57,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
 
 }
 
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
 /*
  * Generic virtual read/write.  Note that we don't support half-word
  * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
@@ -125,7 +128,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen);
  * only.  Their primary purpose is to access PCI and ISA peripherals.
  *
  * Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerious
+ * big endian mode connectivity is in place, as described by numerous
  * ARM documents:
  *
  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31