X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=include%2Faltera.h;h=22d55cfd73e70dd17a979d1dc8d508053bd4f29e;hb=4df0292359311c1e1e12f83cd7d70e7235edefe8;hp=88f72db03cd992d82b7e4b63c03b3501ab92bc8a;hpb=c609719b8d1b2dca590e0ed499016d041203e403;p=oweals%2Fu-boot.git diff --git a/include/altera.h b/include/altera.h index 88f72db03c..22d55cfd73 100644 --- a/include/altera.h +++ b/include/altera.h @@ -1,25 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * */ #include @@ -28,46 +10,118 @@ #define _ALTERA_H_ /* - * Note that this is just Altera FPGA interface boilerplate. - * There is no support for Altera devices yet. - * - * See include/xilinx.h for a working example. + * For the StratixV FPGA programming via SPI, the following + * information is coded in the 32bit cookie: + * Bit 31 ... Bit 0 + * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin */ +#define FPGA_COOKIE(bus, dev, config, done) \ + (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done)) +#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff) +#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff) +#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff) +#define COOKIE2DONE(c) ((c) & 0xff) -/* In your board's config.h file you should define CONFIG_FPGA as such: - * #define CONFIG_FPGA (CFG_ALTERA_xxx | CFG_ALTERA_IF_xxx ) - */ +enum altera_iface { + /* insert all new types after this */ + min_altera_iface_type, + /* serial data and external clock */ + passive_serial, + /* parallel data */ + passive_parallel_synchronous, + /* parallel data */ + passive_parallel_asynchronous, + /* serial data w/ internal clock (not used) */ + passive_serial_asynchronous, + /* jtag/tap serial (not used ) */ + altera_jtag_mode, + /* fast passive parallel (FPP) */ + fast_passive_parallel, + /* fast passive parallel with security (FPPS) */ + fast_passive_parallel_security, + /* secure device manager (SDM) mailbox */ + secure_device_manager_mailbox, + /* insert all new types before this */ + max_altera_iface_type, +}; + +enum altera_family { + /* insert all new types after this */ + min_altera_type, + /* ACEX1K Family */ + Altera_ACEX1K, + /* CYCLONII Family */ + Altera_CYC2, + /* StratixII Family */ + Altera_StratixII, + /* StratixV Family */ + Altera_StratixV, + /* Stratix10 Family */ + Intel_FPGA_Stratix10, + /* SoCFPGA Family */ + Altera_SoCFPGA, + + /* Add new models here */ + + /* insert all new types before this */ + max_altera_type, +}; + +typedef struct { + /* part type */ + enum altera_family family; + /* interface type */ + enum altera_iface iface; + /* bytes of data part can accept */ + size_t size; + /* interface function table */ + void *iface_fns; + /* base interface address */ + void *base; + /* implementation specific cookie */ + int cookie; +} Altera_desc; -/* Altera Model definitions */ -#define CFG_ALTERA_xxxx ( CFG_FPGA_ALTERA | CFG_FPGA_DEV( 0x1 )) -/* Add new models here */ +/* Generic Altera Functions + *********************************************************************/ +extern int altera_load(Altera_desc *desc, const void *image, size_t size); +extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize); +extern int altera_info(Altera_desc *desc); -/* Altera Interface definitions */ -#define CFG_ALTERA_IF_xxx CFG_FPGA_IF( 0x1 ) -/* Add new interfaces here */ +/* Board specific implementation specific function types + *********************************************************************/ +typedef int (*Altera_pre_fn)( int cookie ); +typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie ); +typedef int (*Altera_status_fn)( int cookie ); +typedef int (*Altera_done_fn)( int cookie ); +typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); +typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); +typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie); +typedef int (*Altera_abort_fn)( int cookie ); +typedef int (*Altera_post_fn)( int cookie ); -typedef enum { /* typedef Altera_iface */ - min_altera_iface_type, /* insert all new types after this */ -/* Add new interfaces here */ - max_altera_iface_type /* insert all new types before this */ -} Altera_iface; /* end, typedef Altera_iface */ +typedef struct { + Altera_pre_fn pre; + Altera_config_fn config; + Altera_status_fn status; + Altera_done_fn done; + Altera_clk_fn clk; + Altera_data_fn data; + Altera_write_fn write; + Altera_abort_fn abort; + Altera_post_fn post; +} altera_board_specific_func; -typedef enum { /* typedef Altera_Family */ - min_altera_type, /* insert all new types after this */ -/* Add new models here */ - max_altera_type /* insert all new types before this */ -} Altera_Family; /* end, typedef Altera_Family */ +#ifdef CONFIG_FPGA_SOCFPGA +int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif -typedef struct { /* typedef Altera_desc */ - Altera_Family family; /* part type */ - Altera_iface iface; /* interface type */ - size_t size; /* bytes of data part can accept */ - void * base; /* base interface address */ -} Altera_desc; /* end, typedef Altera_desc */ +#ifdef CONFIG_FPGA_STRATIX_V +int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif -extern int altera_load( Altera_desc *desc, void *image, size_t size ); -extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int altera_info( Altera_desc *desc ); -extern int altera_reloc( Altera_desc *desc, ulong reloc_off ); +#ifdef CONFIG_FPGA_STRATIX10 +int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); +#endif -#endif /* _ALTERA_H_ */ +#endif /* _ALTERA_H_ */