X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fusb%2Fhost%2Fxhci-fsl.c;h=c0b98a8ec71c3e0a97b996d60f8313c66f92145e;hb=921208ebca6f109990359b3089b5f416b269b07b;hp=bda5b5f9134ac3421126519c1257bc5c7ff179b6;hpb=cbe7706ab8aab06c18edaa9b120371f9c8012728;p=oweals%2Fu-boot.git

diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c
index bda5b5f913..c0b98a8ec7 100644
--- a/drivers/usb/host/xhci-fsl.c
+++ b/drivers/usb/host/xhci-fsl.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015,2016 Freescale Semiconductor, Inc.
  *
  * FSL USB HOST xHCI Controller
  *
  * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -20,9 +19,7 @@
 #include <dm.h>
 
 /* Declare global data pointer */
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_DM_USB
+#if !CONFIG_IS_ENABLED(DM_USB)
 static struct fsl_xhci fsl_xhci;
 unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
 #else
@@ -40,7 +37,8 @@ __weak int __board_usb_init(int index, enum usb_init_type init)
 
 static int erratum_a008751(void)
 {
-#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB)
+#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
+					defined(CONFIG_TARGET_LS2080AQDS)
 	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
 	writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
 	return 0;
@@ -58,6 +56,13 @@ static void fsl_apply_xhci_errata(void)
 	}
 }
 
+static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
+{
+	clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
+			USB3_ENABLE_BEAT_BURST);
+	setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
+}
+
 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
 {
 	int ret = 0;
@@ -74,6 +79,22 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
 	/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
 	dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
 
+	/* Change beat burst and outstanding pipelined transfers requests */
+	fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
+
+	/*
+	 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
+	 * reliably support Rx Detect in P3 mode(P3 is the default
+	 * setting). Therefore, some USB3.0 devices may not be detected
+	 * reliably in Super Speed mode. So, USB controller to configure
+	 * USB in P2 mode whenever the Receive Detect feature is required.
+	 * whenever the Receive Detect feature is required.
+	 */
+	if (has_erratum_a010151())
+		clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
+				DWC3_GUSB3PIPECTL_DISRXDETP3,
+				DWC3_GUSB3PIPECTL_DISRXDETP3);
+
 	return ret;
 }
 
@@ -86,7 +107,7 @@ static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
 	return 0;
 }
 
-#ifdef CONFIG_DM_USB
+#if CONFIG_IS_ENABLED(DM_USB)
 static int xhci_fsl_probe(struct udevice *dev)
 {
 	struct xhci_fsl_priv *priv = dev_get_priv(dev);
@@ -98,7 +119,7 @@ static int xhci_fsl_probe(struct udevice *dev)
 	/*
 	 * Get the base address for XHCI controller from the device node
 	 */
-	priv->hcd_base = dev_get_addr(dev);
+	priv->hcd_base = devfdt_get_addr(dev);
 	if (priv->hcd_base == FDT_ADDR_T_NONE) {
 		debug("Can't get the XHCI register base address\n");
 		return -ENXIO;