X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fspi%2Fstm32_qspi.c;h=3b92254a5ce16adb668ced4e3038a2b5102dd643;hb=cce289a928583a64db6ec8f813cc7884ae62c213;hp=f6cc35336320ce1ec0e5cba4e9f0879e1d34b39d;hpb=c90c43cda8c376f949266f920bbb49119aef0b00;p=oweals%2Fu-boot.git

diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index f6cc353363..3b92254a5c 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -220,7 +220,7 @@ static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
 			cs ? STM32_QSPI_CR_FSEL : 0);
 }
 
-static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
+static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode)
 {
 	unsigned int ccr_reg = 0;
 	u8 imode, admode, dmode;
@@ -229,21 +229,21 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 
 	imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
 	admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
-
-	if (mode & SPI_RX_QUAD) {
-		dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
-		if (mode & SPI_TX_QUAD) {
-			imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
-			admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
-		}
-	} else if (mode & SPI_RX_DUAL) {
-		dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
-		if (mode & SPI_TX_DUAL) {
-			imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
-			admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
+	dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
+
+	if ((priv->command & CMD_HAS_ADR) && (priv->command & CMD_HAS_DATA)) {
+		if (fmode == STM32_QSPI_CCR_IND_WRITE) {
+			if (mode & SPI_TX_QUAD)
+				dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
+			else if (mode & SPI_TX_DUAL)
+				dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
+		} else if ((fmode == STM32_QSPI_CCR_MEM_MAP) ||
+			 (fmode == STM32_QSPI_CCR_IND_READ)) {
+			if (mode & SPI_RX_QUAD)
+				dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
+			else if (mode & SPI_RX_DUAL)
+				dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
 		}
-	} else {
-		dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
 	}
 
 	if (priv->command & CMD_HAS_DATA)
@@ -258,8 +258,11 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 				<< STM32_QSPI_CCR_ADSIZE_SHIFT);
 		ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
 	}
+
+	ccr_reg |= (fmode << STM32_QSPI_CCR_FMODE_SHIFT);
 	ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
 	ccr_reg |= cmd;
+
 	return ccr_reg;
 }
 
@@ -272,8 +275,7 @@ static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
 			| CMD_HAS_DUMMY;
 	priv->dummycycles = flash->dummy_byte * 8;
 
-	ccr_reg = _stm32_qspi_gen_ccr(priv);
-	ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
+	ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);
 
 	_stm32_qspi_wait_for_not_busy(priv);
 
@@ -359,9 +361,8 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 		}
 
 		if (flags & SPI_XFER_END) {
-			ccr_reg = _stm32_qspi_gen_ccr(priv);
-			ccr_reg |= STM32_QSPI_CCR_IND_WRITE
-					<< STM32_QSPI_CCR_FMODE_SHIFT;
+			ccr_reg = _stm32_qspi_gen_ccr(priv,
+						      STM32_QSPI_CCR_IND_WRITE);
 
 			_stm32_qspi_wait_for_not_busy(priv);
 
@@ -392,9 +393,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 			}
 		}
 	} else if (din) {
-		ccr_reg = _stm32_qspi_gen_ccr(priv);
-		ccr_reg |= STM32_QSPI_CCR_IND_READ
-				<< STM32_QSPI_CCR_FMODE_SHIFT;
+		ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ);
 
 		_stm32_qspi_wait_for_not_busy(priv);