X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fspi%2Fstm32_qspi.c;h=3b92254a5ce16adb668ced4e3038a2b5102dd643;hb=cce289a928583a64db6ec8f813cc7884ae62c213;hp=558708a4a7b0e26cc57850b6552f6c83ff9317a7;hpb=aa5e3e22f4d648c09b6b63eac8eec8d7a2fc2994;p=oweals%2Fu-boot.git diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 558708a4a7..3b92254a5c 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -1,24 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 * * Michael Kurz, * * STM32 QSPI driver - * - * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include +#include #include +#include #include #include #include -#include -#include #include -#include - -DECLARE_GLOBAL_DATA_PTR; +#include struct stm32_qspi_regs { u32 cr; /* 0x00 */ @@ -156,6 +155,8 @@ enum STM32_QSPI_CCR_FMODE { /* default SCK frequency, unit: HZ */ #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000 +#define STM32_MAX_NORCHIP 2 + struct stm32_qspi_platdata { u32 base; u32 memory_map; @@ -207,12 +208,19 @@ static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv) static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size) { u32 fsize = fls(size) - 1; + clrsetbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT, fsize << STM32_QSPI_DCR_FSIZE_SHIFT); } -static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) +static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs) +{ + clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL, + cs ? STM32_QSPI_CR_FSEL : 0); +} + +static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode) { unsigned int ccr_reg = 0; u8 imode, admode, dmode; @@ -221,21 +229,21 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) imode = STM32_QSPI_CCR_IMODE_ONE_LINE; admode = STM32_QSPI_CCR_ADMODE_ONE_LINE; - - if (mode & SPI_RX_QUAD) { - dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE; - if (mode & SPI_TX_QUAD) { - imode = STM32_QSPI_CCR_IMODE_FOUR_LINE; - admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE; + dmode = STM32_QSPI_CCR_DMODE_ONE_LINE; + + if ((priv->command & CMD_HAS_ADR) && (priv->command & CMD_HAS_DATA)) { + if (fmode == STM32_QSPI_CCR_IND_WRITE) { + if (mode & SPI_TX_QUAD) + dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE; + else if (mode & SPI_TX_DUAL) + dmode = STM32_QSPI_CCR_DMODE_TWO_LINE; + } else if ((fmode == STM32_QSPI_CCR_MEM_MAP) || + (fmode == STM32_QSPI_CCR_IND_READ)) { + if (mode & SPI_RX_QUAD) + dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE; + else if (mode & SPI_RX_DUAL) + dmode = STM32_QSPI_CCR_DMODE_TWO_LINE; } - } else if (mode & SPI_RX_DUAL) { - dmode = STM32_QSPI_CCR_DMODE_TWO_LINE; - if (mode & SPI_TX_DUAL) { - imode = STM32_QSPI_CCR_IMODE_TWO_LINE; - admode = STM32_QSPI_CCR_ADMODE_TWO_LINE; - } - } else { - dmode = STM32_QSPI_CCR_DMODE_ONE_LINE; } if (priv->command & CMD_HAS_DATA) @@ -250,20 +258,24 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) << STM32_QSPI_CCR_ADSIZE_SHIFT); ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT); } + + ccr_reg |= (fmode << STM32_QSPI_CCR_FMODE_SHIFT); ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT); ccr_reg |= cmd; + return ccr_reg; } static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv, - struct spi_flash *flash) + struct spi_flash *flash) { + unsigned int ccr_reg; + priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA | CMD_HAS_DUMMY; priv->dummycycles = flash->dummy_byte * 8; - unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv); - ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT); + ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP); _stm32_qspi_wait_for_not_busy(priv); @@ -292,10 +304,12 @@ static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg) } static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, - struct spi_flash *flash, unsigned int bitlen, - const u8 *dout, u8 *din, unsigned long flags) + struct spi_flash *flash, unsigned int bitlen, + const u8 *dout, u8 *din, unsigned long flags) { unsigned int words = bitlen / 8; + u32 ccr_reg; + int i; if (flags & SPI_XFER_MMAP) { _stm32_qspi_enable_mmap(priv, flash); @@ -347,9 +361,8 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, } if (flags & SPI_XFER_END) { - u32 ccr_reg = _stm32_qspi_gen_ccr(priv); - ccr_reg |= STM32_QSPI_CCR_IND_WRITE - << STM32_QSPI_CCR_FMODE_SHIFT; + ccr_reg = _stm32_qspi_gen_ccr(priv, + STM32_QSPI_CCR_IND_WRITE); _stm32_qspi_wait_for_not_busy(priv); @@ -366,7 +379,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, debug("%s: words:%d data:", __func__, words); - int i = 0; + i = 0; while (words > i) { writeb(dout[i], &priv->regs->dr); debug("%02x ", dout[i]); @@ -380,9 +393,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, } } } else if (din) { - u32 ccr_reg = _stm32_qspi_gen_ccr(priv); - ccr_reg |= STM32_QSPI_CCR_IND_READ - << STM32_QSPI_CCR_FMODE_SHIFT; + ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ); _stm32_qspi_wait_for_not_busy(priv); @@ -395,7 +406,7 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, debug("%s: data:", __func__); - int i = 0; + i = 0; while (words > i) { din[i] = readb(&priv->regs->dr); debug("%02x ", din[i]); @@ -409,27 +420,23 @@ static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv, static int stm32_qspi_ofdata_to_platdata(struct udevice *bus) { - struct fdt_resource res_regs, res_mem; + struct resource res_regs, res_mem; struct stm32_qspi_platdata *plat = bus->platdata; - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); int ret; - ret = fdt_get_named_resource(blob, node, "reg", "reg-names", - "QuadSPI", &res_regs); + ret = dev_read_resource_byname(bus, "qspi", &res_regs); if (ret) { debug("Error: can't get regs base addresses(ret = %d)!\n", ret); return -ENOMEM; } - ret = fdt_get_named_resource(blob, node, "reg", "reg-names", - "QuadSPI-memory", &res_mem); + ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem); if (ret) { debug("Error: can't get mmap base address(ret = %d)!\n", ret); return -ENOMEM; } - plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", - STM32_QSPI_DEFAULT_SCK_FREQ); + plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency", + STM32_QSPI_DEFAULT_SCK_FREQ); plat->base = res_regs.start; plat->memory_map = res_mem.start; @@ -449,6 +456,9 @@ static int stm32_qspi_probe(struct udevice *bus) struct stm32_qspi_platdata *plat = dev_get_platdata(bus); struct stm32_qspi_priv *priv = dev_get_priv(bus); struct dm_spi_bus *dm_spi_bus; + struct clk clk; + struct reset_ctl reset_ctl; + int ret; dm_spi_bus = bus->uclass_priv; @@ -458,9 +468,6 @@ static int stm32_qspi_probe(struct udevice *bus) priv->max_hz = plat->max_hz; -#ifdef CONFIG_CLK - int ret; - struct clk clk; ret = clk_get_by_index(bus, 0, &clk); if (ret < 0) return ret; @@ -478,7 +485,19 @@ static int stm32_qspi_probe(struct udevice *bus) return priv->clock_rate; } -#endif + ret = reset_get_by_index(bus, 0, &reset_ctl); + if (ret) { + if (ret != -ENOENT) { + dev_err(bus, "failed to get reset\n"); + clk_disable(&clk); + return ret; + } + } else { + /* Reset QSPI controller */ + reset_assert(&reset_ctl); + udelay(2); + reset_deassert(&reset_ctl); + } setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); @@ -495,10 +514,17 @@ static int stm32_qspi_claim_bus(struct udevice *dev) struct stm32_qspi_priv *priv; struct udevice *bus; struct spi_flash *flash; + struct dm_spi_slave_platdata *slave_plat; bus = dev->parent; priv = dev_get_priv(bus); flash = dev_get_uclass_priv(dev); + slave_plat = dev_get_parent_platdata(dev); + + if (slave_plat->cs >= STM32_MAX_NORCHIP) + return -ENODEV; + + _stm32_qspi_set_cs(priv, slave_plat->cs); _stm32_qspi_set_flash_size(priv, flash->size); @@ -521,7 +547,7 @@ static int stm32_qspi_release_bus(struct udevice *dev) } static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) + const void *dout, void *din, unsigned long flags) { struct stm32_qspi_priv *priv; struct udevice *bus; @@ -539,12 +565,13 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) { struct stm32_qspi_platdata *plat = bus->platdata; struct stm32_qspi_priv *priv = dev_get_priv(bus); + u32 qspi_clk = priv->clock_rate; + u32 prescaler = 255; + u32 csht; if (speed > plat->max_hz) speed = plat->max_hz; - u32 qspi_clk = priv->clock_rate; - u32 prescaler = 255; if (speed > 0) { prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; if (prescaler > 255) @@ -553,7 +580,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) prescaler = 0; } - u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000); + csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000); csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK; _stm32_qspi_wait_for_not_busy(priv); @@ -563,7 +590,6 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) STM32_QSPI_CR_PRESCALER_SHIFT, prescaler << STM32_QSPI_CR_PRESCALER_SHIFT); - clrsetbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT, csht << STM32_QSPI_DCR_CSHT_SHIFT); @@ -633,6 +659,7 @@ static const struct dm_spi_ops stm32_qspi_ops = { static const struct udevice_id stm32_qspi_ids[] = { { .compatible = "st,stm32-qspi" }, + { .compatible = "st,stm32f469-qspi" }, { } };