X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fserial%2Fserial_zynq.c;h=88bebed23638c665d8b496889975f7ee2336717a;hb=1c5e6b6fbb3835b1170c01844c862c0eaa9bffed;hp=35bbebe7056bbd72ac71295472eb7466aac83dec;hpb=89143fb3b0cc9897b7aa9ec8b6028a6c624887d4;p=oweals%2Fu-boot.git diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 35bbebe705..88bebed236 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -2,32 +2,25 @@ * Copyright (C) 2012 Michal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include +#include +#include #include #include #include #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ @@ -37,55 +30,32 @@ #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ -/* Some clock/baud constants */ -#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ -#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ - struct uart_zynq { - u32 control; /* Control Register [8:0] */ - u32 mode; /* Mode Register [10:0] */ + u32 control; /* 0x0 - Control Register [8:0] */ + u32 mode; /* 0x4 - Mode Register [10:0] */ u32 reserved1[4]; - u32 baud_rate_gen; /* Baud Rate Generator [15:0] */ + u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ u32 reserved2[4]; - u32 channel_sts; /* Channel Status [11:0] */ - u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */ - u32 baud_rate_divider; /* Baud Rate Divider [7:0] */ + u32 channel_sts; /* 0x2c - Channel Status [11:0] */ + u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ + u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ }; -static struct uart_zynq *uart_zynq_ports[2] = { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 - [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, -#endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 - [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, -#endif -}; - -struct uart_zynq_params { - u32 baudrate; - u32 clock; -}; - -static struct uart_zynq_params uart_zynq_ports_param[2] = { -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) - [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, - [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, -#endif -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) - [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, - [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, -#endif +struct zynq_uart_priv { + struct uart_zynq *regs; }; /* Set up the baud rate in gd struct */ -static void uart_zynq_serial_setbrg(const int port) +static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, + unsigned long clock, unsigned long baud) { /* Calculation results. */ unsigned int calc_bauderror, bdiv, bgen; unsigned long calc_baud = 0; - unsigned long baud = uart_zynq_ports_param[port].baudrate; - unsigned long clock = uart_zynq_ports_param[port].clock; - struct uart_zynq *regs = uart_zynq_ports[port]; + + /* Covering case where input clock is so slow */ + if (clock < 1000000 && baud > 4800) + baud = 4800; /* master clock * Baud rate = ------------------ @@ -117,131 +87,131 @@ static void uart_zynq_serial_setbrg(const int port) } /* Initialize the UART, with...some settings. */ -static int uart_zynq_serial_init(const int port) +static void _uart_zynq_serial_init(struct uart_zynq *regs) { - struct uart_zynq *regs = uart_zynq_ports[port]; - - if (!regs) - return -1; - /* RX/TX enabled & reset */ writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ ZYNQ_UART_CR_RXRST, ®s->control); writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ - uart_zynq_serial_setbrg(port); - - return 0; } -static void uart_zynq_serial_putc(const char c, const int port) +static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - struct uart_zynq *regs = uart_zynq_ports[port]; - - while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) - WATCHDOG_RESET(); + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) + return -EAGAIN; - if (c == '\n') { - writel('\r', ®s->tx_rx_fifo); - while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0) - WATCHDOG_RESET(); - } writel(c, ®s->tx_rx_fifo); + + return 0; } -static void uart_zynq_serial_puts(const char *s, const int port) +int zynq_serial_setbrg(struct udevice *dev, int baudrate) { - while (*s) - uart_zynq_serial_putc(*s++, port); + struct zynq_uart_priv *priv = dev_get_priv(dev); + unsigned long clock = get_uart_clk(0); + + _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); + + return 0; } -static int uart_zynq_serial_tstc(const int port) +static int zynq_serial_probe(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_priv *priv = dev_get_priv(dev); - return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; + _uart_zynq_serial_init(priv->regs); + + return 0; } -static int uart_zynq_serial_getc(const int port) +static int zynq_serial_getc(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_priv *priv = dev_get_priv(dev); + struct uart_zynq *regs = priv->regs; + + if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) + return -EAGAIN; - while (!uart_zynq_serial_tstc(port)) - WATCHDOG_RESET(); return readl(®s->tx_rx_fifo); } -#if !defined(CONFIG_SERIAL_MULTI) -int serial_init(void) +static int zynq_serial_putc(struct udevice *dev, const char ch) { - return uart_zynq_serial_init(0); -} + struct zynq_uart_priv *priv = dev_get_priv(dev); -void serial_setbrg(void) -{ - uart_zynq_serial_setbrg(0); + return _uart_zynq_serial_putc(priv->regs, ch); } -void serial_putc(const char c) +static int zynq_serial_pending(struct udevice *dev, bool input) { - uart_zynq_serial_putc(c, 0); -} + struct zynq_uart_priv *priv = dev_get_priv(dev); + struct uart_zynq *regs = priv->regs; -void serial_puts(const char *s) -{ - uart_zynq_serial_puts(s, 0); + if (input) + return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); + else + return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); } -int serial_getc(void) +static int zynq_serial_ofdata_to_platdata(struct udevice *dev) { - return uart_zynq_serial_getc(0); + struct zynq_uart_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = (struct uart_zynq *)addr; + + return 0; } -int serial_tstc(void) +static const struct dm_serial_ops zynq_serial_ops = { + .putc = zynq_serial_putc, + .pending = zynq_serial_pending, + .getc = zynq_serial_getc, + .setbrg = zynq_serial_setbrg, +}; + +static const struct udevice_id zynq_serial_ids[] = { + { .compatible = "xlnx,xuartps" }, + { .compatible = "cdns,uart-r1p8" }, + { } +}; + +U_BOOT_DRIVER(serial_s5p) = { + .name = "serial_zynq", + .id = UCLASS_SERIAL, + .of_match = zynq_serial_ids, + .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), + .probe = zynq_serial_probe, + .ops = &zynq_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_ZYNQ + +#include + +void _debug_uart_init(void) { - return uart_zynq_serial_tstc(0); -} -#else -/* Multi serial device functions */ -#define DECLARE_PSSERIAL_FUNCTIONS(port) \ - int uart_zynq##port##_init(void) \ - { return uart_zynq_serial_init(port); } \ - void uart_zynq##port##_setbrg(void) \ - { return uart_zynq_serial_setbrg(port); } \ - int uart_zynq##port##_getc(void) \ - { return uart_zynq_serial_getc(port); } \ - int uart_zynq##port##_tstc(void) \ - { return uart_zynq_serial_tstc(port); } \ - void uart_zynq##port##_putc(const char c) \ - { uart_zynq_serial_putc(c, port); } \ - void uart_zynq##port##_puts(const char *s) \ - { uart_zynq_serial_puts(s, port); } - -/* Serial device descriptor */ -#define INIT_PSSERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = uart_zynq##port##_init, \ - .stop = NULL, \ - .setbrg = uart_zynq##port##_setbrg, \ - .getc = uart_zynq##port##_getc, \ - .tstc = uart_zynq##port##_tstc, \ - .putc = uart_zynq##port##_putc, \ - .puts = uart_zynq##port##_puts, \ -} + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; -DECLARE_PSSERIAL_FUNCTIONS(0); -struct serial_device uart_zynq_serial0_device = - INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); -DECLARE_PSSERIAL_FUNCTIONS(1); -struct serial_device uart_zynq_serial1_device = - INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); + _uart_zynq_serial_init(regs); + _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); +} -__weak struct serial_device *default_serial_console(void) +static inline void _debug_uart_putc(int ch) { - if (uart_zynq_ports[0]) - return &uart_zynq_serial0_device; - if (uart_zynq_ports[1]) - return &uart_zynq_serial1_device; + struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; - return NULL; + while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); } + +DEBUG_UART_FUNCS + #endif