X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fserial%2Fns16550.c;h=6cf2be8f2b892eb0fd7cfea13ddf825b4380724b;hb=29e9363504d6e2aef0bd11a08de59cf635e285bc;hp=eb00f1ca8a254bdd7178e61f1c15c114a7ac2336;hpb=21d004368fc8a4da07147c58dfe9a4e16d4ab761;p=oweals%2Fu-boot.git diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index eb00f1ca8a..6cf2be8f2b 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -5,10 +5,11 @@ */ #include +#include #include #include -#include #include +#include #include #include #include @@ -19,9 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ -#define UART_FCRVAL (UART_FCR_FIFO_EN | \ - UART_FCR_RXSR | \ - UART_FCR_TXSR) /* Clear & enable FIFOs */ #ifndef CONFIG_DM_SERIAL #ifdef CONFIG_SYS_NS16550_PORT_MAPPED @@ -54,16 +52,16 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_SYS_NS16550_IER 0x00 #endif /* CONFIG_SYS_NS16550_IER */ -#ifdef CONFIG_DM_SERIAL - -static inline void serial_out_shift(unsigned char *addr, int shift, int value) +static inline void serial_out_shift(void *addr, int shift, int value) { #ifdef CONFIG_SYS_NS16550_PORT_MAPPED outb(value, (ulong)addr); -#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) out_le32(addr, value); #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) out_be32(addr, value); +#elif defined(CONFIG_SYS_NS16550_MEM32) + writel(value, addr); #elif defined(CONFIG_SYS_BIG_ENDIAN) writeb(value, addr + (1 << shift) - 1); #else @@ -71,33 +69,42 @@ static inline void serial_out_shift(unsigned char *addr, int shift, int value) #endif } -static inline int serial_in_shift(unsigned char *addr, int shift) +static inline int serial_in_shift(void *addr, int shift) { #ifdef CONFIG_SYS_NS16550_PORT_MAPPED return inb((ulong)addr); -#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN) return in_le32(addr); #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) return in_be32(addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) + return readl(addr); #elif defined(CONFIG_SYS_BIG_ENDIAN) - return readb(addr + (1 << reg_shift) - 1); + return readb(addr + (1 << shift) - 1); #else return readb(addr); #endif } +#ifdef CONFIG_DM_SERIAL + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + static void ns16550_writeb(NS16550_t port, int offset, int value) { struct ns16550_platdata *plat = port->plat; unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = map_sysmem(plat->base, 0) + offset; + addr = (unsigned char *)plat->base + offset; + /* * As far as we know it doesn't make sense to support selection of * these options at run-time, so use the existing CONFIG options. */ - serial_out_shift(addr, plat->reg_shift, value); + serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -106,45 +113,48 @@ static int ns16550_readb(NS16550_t port, int offset) unsigned char *addr; offset *= 1 << plat->reg_shift; - addr = map_sysmem(plat->base, 0) + offset; + addr = (unsigned char *)plat->base + offset; + + return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); +} + +static u32 ns16550_getfcr(NS16550_t port) +{ + struct ns16550_platdata *plat = port->plat; - return serial_in_shift(addr, plat->reg_shift); + return plat->fcr; } /* We can clean these up once everything is moved to driver model */ #define serial_out(value, addr) \ - ns16550_writeb(com_port, addr - (unsigned char *)com_port, value) + ns16550_writeb(com_port, \ + (unsigned char *)addr - (unsigned char *)com_port, value) #define serial_in(addr) \ - ns16550_readb(com_port, addr - (unsigned char *)com_port) -#endif - -static inline int calc_divisor(NS16550_t port, int clock, int baudrate) + ns16550_readb(com_port, \ + (unsigned char *)addr - (unsigned char *)com_port) +#else +static u32 ns16550_getfcr(NS16550_t port) { - const unsigned int mode_x_div = 16; - - return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); + return UART_FCR_DEFVAL; } +#endif int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) { -#ifdef CONFIG_OMAP1510 - /* If can't cleanly clock 115200 set div to 1 */ - if ((clock == 12000000) && (baudrate == 115200)) { - port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ - return 1; /* return 1 for base divisor */ - } - port->osc_12m_sel = 0; /* clear if previsouly set */ -#endif + const unsigned int mode_x_div = 16; - return calc_divisor(port, clock, baudrate); + return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); } static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) { - serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + /* to keep serial format, read lcr before writing BKSE */ + int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; + + serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr); serial_out(baud_divisor & 0xff, &com_port->dll); serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); - serial_out(UART_LCRVAL, &com_port->lcr); + serial_out(lcr_val, &com_port->lcr); } void NS16550_init(NS16550_t com_port, int baud_divisor) @@ -168,22 +178,21 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) ; serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); -#if defined(CONFIG_OMAP) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) +#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif - NS16550_setbrg(com_port, 0); + serial_out(UART_MCRVAL, &com_port->mcr); - serial_out(UART_FCRVAL, &com_port->fcr); + serial_out(ns16550_getfcr(com_port), &com_port->fcr); + /* initialize serial config to 8N1 before writing baudrate */ + serial_out(UART_LCRVAL, &com_port->lcr); if (baud_divisor != -1) NS16550_setbrg(com_port, baud_divisor); -#if defined(CONFIG_OMAP) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ - defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) - +#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \ + defined(CONFIG_OMAP_SERIAL) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); -#endif /* CONFIG_OMAP */ +#endif #if defined(CONFIG_SOC_KEYSTONE) serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); #endif @@ -195,7 +204,7 @@ void NS16550_reinit(NS16550_t com_port, int baud_divisor) serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); NS16550_setbrg(com_port, 0); serial_out(UART_MCRVAL, &com_port->mcr); - serial_out(UART_FCRVAL, &com_port->fcr); + serial_out(ns16550_getfcr(com_port), &com_port->fcr); NS16550_setbrg(com_port, baud_divisor); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ @@ -240,7 +249,7 @@ int NS16550_tstc(NS16550_t com_port) #include -void debug_uart_init(void) +static inline void _debug_uart_init(void) { struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; int baud_divisor; @@ -251,26 +260,41 @@ void debug_uart_init(void) * feasible. The better fix is to move all users of this driver to * driver model. */ - baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, - CONFIG_BAUDRATE); + baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); + serial_dout(&com_port->mcr, UART_MCRVAL); + serial_dout(&com_port->fcr, UART_FCR_DEFVAL); + + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + serial_dout(&com_port->dll, baud_divisor & 0xff); + serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + serial_dout(&com_port->lcr, UART_LCRVAL); +} + +static inline int NS16550_read_baud_divisor(struct NS16550 *com_port) +{ + int ret; - serial_out_shift(&com_port->ier, 0, CONFIG_SYS_NS16550_IER); - serial_out_shift(&com_port->mcr, 0, UART_MCRVAL); - serial_out_shift(&com_port->fcr, 0, UART_FCRVAL); + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + ret = serial_din(&com_port->dll) & 0xff; + ret |= (serial_din(&com_port->dlm) & 0xff) << 8; + serial_dout(&com_port->lcr, UART_LCRVAL); - serial_out_shift(&com_port->lcr, 0, UART_LCR_BKSE | UART_LCRVAL); - serial_out_shift(&com_port->dll, 0, baud_divisor & 0xff); - serial_out_shift(&com_port->dlm, 0, (baud_divisor >> 8) & 0xff); - serial_out_shift(&com_port->lcr, 0, UART_LCRVAL); + return ret; } static inline void _debug_uart_putc(int ch) { struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; - while (!(serial_in_shift(&com_port->lsr, 0) & UART_LSR_THRE)) - ; - serial_out_shift(&com_port->thr, 0, ch); + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) { +#ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED + if (!NS16550_read_baud_divisor(com_port)) + return; +#endif + } + serial_dout(&com_port->thr, ch); } DEBUG_UART_FUNCS @@ -303,9 +327,9 @@ static int ns16550_serial_pending(struct udevice *dev, bool input) struct NS16550 *const com_port = dev_get_priv(dev); if (input) - return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; + return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0; else - return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1; + return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1; } static int ns16550_serial_getc(struct udevice *dev) @@ -331,9 +355,67 @@ static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) return 0; } +static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + int lcr_val = UART_LCR_WLS_8; + uint parity = SERIAL_GET_PARITY(serial_config); + uint bits = SERIAL_GET_BITS(serial_config); + uint stop = SERIAL_GET_STOP(serial_config); + + /* + * only parity config is implemented, check if other serial settings + * are the default one. + */ + if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP) + return -ENOTSUPP; /* not supported in driver*/ + + switch (parity) { + case SERIAL_PAR_NONE: + /* no bits to add */ + break; + case SERIAL_PAR_ODD: + lcr_val |= UART_LCR_PEN; + break; + case SERIAL_PAR_EVEN: + lcr_val |= UART_LCR_PEN | UART_LCR_EPS; + break; + default: + return -ENOTSUPP; /* not supported in driver*/ + } + + serial_out(lcr_val, &com_port->lcr); + return 0; +} + +static int ns16550_serial_getinfo(struct udevice *dev, + struct serial_device_info *info) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + struct ns16550_platdata *plat = com_port->plat; + + info->type = SERIAL_CHIP_16550_COMPATIBLE; +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + info->addr_space = SERIAL_ADDRESS_SPACE_IO; +#else + info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY; +#endif + info->addr = plat->base; + info->reg_width = plat->reg_width; + info->reg_shift = plat->reg_shift; + info->reg_offset = plat->reg_offset; + return 0; +} + int ns16550_serial_probe(struct udevice *dev) { struct NS16550 *const com_port = dev_get_priv(dev); + struct reset_ctl_bulk reset_bulk; + int ret; + + ret = reset_get_bulk(dev, &reset_bulk); + if (!ret) + reset_deassert_bulk(&reset_bulk); com_port->plat = dev_get_platdata(dev); NS16550_init(com_port, -1); @@ -341,15 +423,25 @@ int ns16550_serial_probe(struct udevice *dev) return 0; } -#ifdef CONFIG_OF_CONTROL +#if CONFIG_IS_ENABLED(OF_CONTROL) +enum { + PORT_NS16550 = 0, + PORT_JZ4780, +}; +#endif + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) int ns16550_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; + const u32 port_type = dev_get_driver_data(dev); fdt_addr_t addr; + struct clk clk; + int err; /* try Processor Local Bus device first */ - addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); -#ifdef CONFIG_PCI + addr = dev_read_addr(dev); +#if CONFIG_IS_ENABLED(PCI) && defined(CONFIG_DM_PCI) if (addr == FDT_ADDR_T_NONE) { /* then try pci device */ struct fdt_pci_addr pci_addr; @@ -357,21 +449,20 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) int ret; /* we prefer to use a memory-mapped register */ - ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, + ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev), FDT_PCI_SPACE_MEM32, "reg", &pci_addr); if (ret) { /* try if there is any i/o-mapped register */ ret = fdtdec_get_pci_addr(gd->fdt_blob, - dev->of_offset, + dev_of_offset(dev), FDT_PCI_SPACE_IO, "reg", &pci_addr); if (ret) return ret; } - ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset, - &pci_addr, &bar); + ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar); if (ret) return ret; @@ -382,9 +473,37 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED plat->base = addr; - plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "reg-shift", 1); +#else + plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); +#endif + + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); + plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); + plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + plat->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("ns16550 failed to get clock\n"); + return err; + } + + if (!plat->clock) + plat->clock = dev_read_u32_default(dev, "clock-frequency", + CONFIG_SYS_NS16550_CLK); + if (!plat->clock) { + debug("ns16550 clock not defined\n"); + return -EINVAL; + } + + plat->fcr = UART_FCR_DEFVAL; + if (port_type == PORT_JZ4780) + plat->fcr |= UART_FCR_UME; return 0; } @@ -395,5 +514,46 @@ const struct dm_serial_ops ns16550_serial_ops = { .pending = ns16550_serial_pending, .getc = ns16550_serial_getc, .setbrg = ns16550_serial_setbrg, + .setconfig = ns16550_serial_setconfig, + .getinfo = ns16550_serial_getinfo, }; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +/* + * Please consider existing compatible strings before adding a new + * one to keep this table compact. Or you may add a generic "ns16550" + * compatible string to your dts. + */ +static const struct udevice_id ns16550_serial_ids[] = { + { .compatible = "ns16550", .data = PORT_NS16550 }, + { .compatible = "ns16550a", .data = PORT_NS16550 }, + { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, + { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, + { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, + {} +}; +#endif /* OF_CONTROL && !OF_PLATDATA */ + +#if CONFIG_IS_ENABLED(SERIAL_PRESENT) + +/* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */ +#if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL) +U_BOOT_DRIVER(ns16550_serial) = { + .name = "ns16550_serial", + .id = UCLASS_SERIAL, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = ns16550_serial_ids, + .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), +#endif + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, +#if !CONFIG_IS_ENABLED(OF_CONTROL) + .flags = DM_FLAG_PRE_RELOC, +#endif +}; +#endif +#endif /* SERIAL_PRESENT */ + #endif /* CONFIG_DM_SERIAL */