X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fserial%2Farm_dcc.c;h=07981e18ee4991cfdbdcb93036ef996909b7791d;hb=1113ad49dce7d56429c6ad37738d06e7aef21fac;hp=5a7fb6bc00381afa2bfdf7f8198ecd64999c7a33;hpb=cea221116aa305dbf43625513a1210b89116262b;p=oweals%2Fu-boot.git diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index 5a7fb6bc00..07981e18ee 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -1,19 +1,9 @@ /* * Copyright (C) 2004-2007 ARM Limited. * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD + * Copyright (C) 2015 - 2016 Xilinx, Inc, Michal Simek * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0 * * As a special exception, if other files instantiate templates or use macros * or inline functions from this file, or you compile this file and link it @@ -27,200 +17,160 @@ */ #include -#include +#include +#include -#define DCC_ARM9_RBIT (1 << 0) -#define DCC_ARM9_WBIT (1 << 1) -#define DCC_ARM11_RBIT (1 << 30) -#define DCC_ARM11_WBIT (1 << 29) +#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7) +/* + * ARMV6 & ARMV7 + */ +#define DCC_RBIT (1 << 30) +#define DCC_WBIT (1 << 29) -#define read_core_id(x) do { \ - __asm__ ("mrc p15, 0, %0, c0, c0, 0\n" : "=r" (x)); \ - x = (x >> 4) & 0xFFF; \ - } while (0); +#define write_dcc(x) \ + __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x)) +#define read_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x)) + +#define status_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x)) + +#elif defined(CONFIG_CPU_XSCALE) /* - * ARM9 + * XSCALE */ -#define write_arm9_dcc(x) \ - __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x)) - -#define read_arm9_dcc(x) \ - __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x)) +#define DCC_RBIT (1 << 31) +#define DCC_WBIT (1 << 28) -#define status_arm9_dcc(x) \ - __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x)) +#define write_dcc(x) \ + __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x)) -#define can_read_arm9_dcc(x) do { \ - status_arm9_dcc(x); \ - x &= DCC_ARM9_RBIT; \ - } while (0); +#define read_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x)) -#define can_write_arm9_dcc(x) do { \ - status_arm9_dcc(x); \ - x &= DCC_ARM9_WBIT; \ - x = (x == 0); \ - } while (0); +#define status_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x)) +#elif defined(CONFIG_CPU_ARMV8) /* - * ARM11 + * ARMV8 */ -#define write_arm11_dcc(x) \ - __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x)) +#define DCC_RBIT (1 << 30) +#define DCC_WBIT (1 << 29) -#define read_arm11_dcc(x) \ - __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x)) +#define write_dcc(x) \ + __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x)) -#define status_arm11_dcc(x) \ - __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x)) +#define read_dcc(x) \ + __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x)) -#define can_read_arm11_dcc(x) do { \ - status_arm11_dcc(x); \ - x &= DCC_ARM11_RBIT; \ - } while (0); +#define status_dcc(x) \ + __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x)) -#define can_write_arm11_dcc(x) do { \ - status_arm11_dcc(x); \ - x &= DCC_ARM11_WBIT; \ - x = (x == 0); \ - } while (0); +#else +#define DCC_RBIT (1 << 0) +#define DCC_WBIT (1 << 1) -#define TIMEOUT_COUNT 0x4000000 +#define write_dcc(x) \ + __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x)) -static enum { - arm9_and_earlier, - arm11_and_later -} arm_type = arm9_and_earlier; - -#ifndef CONFIG_ARM_DCC_MULTI -#define arm_dcc_init serial_init -void serial_setbrg(void) {} -#define arm_dcc_getc serial_getc -#define arm_dcc_putc serial_putc -#define arm_dcc_puts serial_puts -#define arm_dcc_tstc serial_tstc -#endif +#define read_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x)) -int arm_dcc_init(void) -{ - register unsigned int id; +#define status_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x)) - read_core_id(id); +#endif - if (id >= 0xb00) - arm_type = arm11_and_later; - else - arm_type = arm9_and_earlier; +#define can_read_dcc(x) do { \ + status_dcc(x); \ + x &= DCC_RBIT; \ + } while (0); - return 0; -} +#define can_write_dcc(x) do { \ + status_dcc(x); \ + x &= DCC_WBIT; \ + x = (x == 0); \ + } while (0); -int arm_dcc_getc(void) +#define TIMEOUT_COUNT 0x4000000 + +static int arm_dcc_getc(struct udevice *dev) { int ch; register unsigned int reg; - switch (arm_type) { - case arm11_and_later: - do { - can_read_arm11_dcc(reg); - } while (!reg); - read_arm11_dcc(ch); - break; - - case arm9_and_earlier: - default: - do { - can_read_arm9_dcc(reg); - } while (!reg); - read_arm9_dcc(ch); - break; - } + do { + can_read_dcc(reg); + } while (!reg); + read_dcc(ch); return ch; } -void arm_dcc_putc(char ch) +static int arm_dcc_putc(struct udevice *dev, char ch) { register unsigned int reg; unsigned int timeout_count = TIMEOUT_COUNT; - switch (arm_type) { - case arm11_and_later: - while (--timeout_count) { - can_write_arm11_dcc(reg); - if (reg) - break; - } - if (timeout_count == 0) - return; - else - write_arm11_dcc(ch); - break; - - case arm9_and_earlier: - default: - while (--timeout_count) { - can_write_arm9_dcc(reg); - if (reg) - break; - } - if (timeout_count == 0) - return; - else - write_arm9_dcc(ch); - break; + while (--timeout_count) { + can_write_dcc(reg); + if (reg) + break; } -} + if (timeout_count == 0) + return -EAGAIN; + else + write_dcc(ch); -void arm_dcc_puts(const char *s) -{ - while (*s) - arm_dcc_putc(*s++); + return 0; } -int arm_dcc_tstc(void) +static int arm_dcc_pending(struct udevice *dev, bool input) { register unsigned int reg; - switch (arm_type) { - case arm11_and_later: - can_read_arm11_dcc(reg); - break; - case arm9_and_earlier: - default: - can_read_arm9_dcc(reg); - break; + if (input) { + can_read_dcc(reg); + } else { + can_write_dcc(reg); } return reg; } -#ifdef CONFIG_ARM_DCC_MULTI -static device_t arm_dcc_dev; +static const struct dm_serial_ops arm_dcc_ops = { + .putc = arm_dcc_putc, + .pending = arm_dcc_pending, + .getc = arm_dcc_getc, +}; -int drv_arm_dcc_init(void) -{ - int rc; +static const struct udevice_id arm_dcc_ids[] = { + { .compatible = "arm,dcc", }, + { } +}; - /* Device initialization */ - memset(&arm_dcc_dev, 0, sizeof(arm_dcc_dev)); +U_BOOT_DRIVER(serial_dcc) = { + .name = "arm_dcc", + .id = UCLASS_SERIAL, + .of_match = arm_dcc_ids, + .ops = &arm_dcc_ops, + .flags = DM_FLAG_PRE_RELOC, +}; - strcpy(arm_dcc_dev.name, "dcc"); - arm_dcc_dev.ext = 0; /* No extensions */ - arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT; - arm_dcc_dev.tstc = arm_dcc_tstc; /* 'tstc' function */ - arm_dcc_dev.getc = arm_dcc_getc; /* 'getc' function */ - arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */ - arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */ +#ifdef CONFIG_DEBUG_UART_ARM_DCC - rc = device_register(&arm_dcc_dev); +#include - if (rc == 0) { - arm_dcc_init(); - return 1; - } +static inline void _debug_uart_init(void) +{ +} - return 0; +static inline void _debug_uart_putc(int ch) +{ + arm_dcc_putc(NULL, ch); } + +DEBUG_UART_FUNCS #endif