X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fqe%2Fuec_phy.c;h=69c22dd5e26177c18288b4b7a24933a70af8477d;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=c4214d9a0ae3f64c7cd4a3ae4ab5fba325a8e468;hpb=05c2f4fe2966daa960017a48a506328d01b0a089;p=oweals%2Fu-boot.git

diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index c4214d9a0a..69c22dd5e2 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -1,30 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2005 Freescale Semiconductor, Inc.
+ * Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
  *
  * Author: Shlomi Gridish
  *
  * Description: UCC GETH Driver -- PHY handling
  *		Driver for UEC on QE
  *		Based on 8260_io/fcc_enet.c
- *
- * This program is free software; you can redistribute	it and/or modify it
- * under  the terms of	the GNU General	 Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
  */
 
-#include "common.h"
-#include "net.h"
-#include "malloc.h"
-#include "asm/errno.h"
-#include "asm/immap_qe.h"
-#include "asm/io.h"
-#include "qe.h"
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/immap_qe.h>
+#include <asm/io.h>
 #include "uccf.h"
 #include "uec.h"
 #include "uec_phy.h"
 #include "miiphy.h"
+#include <fsl_qe.h>
+#include <phy.h>
 
 #define ugphy_printk(format, arg...)  \
 	printf(format "\n", ## arg)
@@ -47,7 +44,7 @@
 /*--------------------------------------------------------------------+
  * Fixed PHY (PHY-less) support for Ethernet Ports.
  *
- * Copied from cpu/ppc4xx/4xx_enet.c
+ * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
  *--------------------------------------------------------------------*/
 
 /*
@@ -71,8 +68,8 @@
  *                 {name, speed, duplex},
  *
  *     #define CONFIG_SYS_FIXED_PHY_PORTS \
- *                 CONFIG_SYS_FIXED_PHY_PORT("FSL UEC0",SPEED_100,DUPLEX_FULL) \
- *                 CONFIG_SYS_FIXED_PHY_PORT("FSL UEC2",SPEED_100,DUPLEX_HALF)
+ *                 CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
+ *                 CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
  */
 
 #ifndef CONFIG_FIXED_PHY
@@ -84,7 +81,7 @@
 #endif
 
 struct fixed_phy_port {
-	char name[NAMESIZE];	/* ethernet port name */
+	char name[16];	/* ethernet port name */
 	unsigned int speed;	/* specified speed 10,100 or 1000 */
 	unsigned int duplex;	/* specified duplex FULL or HALF */
 };
@@ -93,6 +90,27 @@ static const struct fixed_phy_port fixed_phy_port[] = {
 	CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
 };
 
+/*--------------------------------------------------------------------+
+ * BitBang MII support for ethernet ports
+ *
+ * Based from MPC8560ADS implementation
+ *--------------------------------------------------------------------*/
+/*
+ * Example board header file to define bitbang ethernet ports:
+ *
+ * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
+ * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
+*/
+#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
+#define CONFIG_SYS_BITBANG_PHY_PORTS	/* default is an empty array */
+#endif
+
+#if defined(CONFIG_BITBANGMII)
+static const char *bitbang_phy_port[] = {
+	CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
+};
+#endif /* CONFIG_BITBANGMII */
+
 static void config_genmii_advert (struct uec_mii_info *mii_info);
 static void genmii_setup_forced (struct uec_mii_info *mii_info);
 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
@@ -100,8 +118,8 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info);
 static int genmii_config_aneg (struct uec_mii_info *mii_info);
 static int genmii_update_link (struct uec_mii_info *mii_info);
 static int genmii_read_status (struct uec_mii_info *mii_info);
-u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
-void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
+u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
+void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
 
 /* Write value to the PHY for this device to the register at regnum, */
 /* waiting until the write is done before it returns.  All PHY */
@@ -113,6 +131,19 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu
 	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
 	u32 tmp_reg;
 
+
+#if defined(CONFIG_BITBANGMII)
+	u32 i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+		if (strncmp(dev->name, bitbang_phy_port[i],
+			sizeof(dev->name)) == 0) {
+			(void)bb_miiphy_write(NULL, mii_id, regnum, value);
+			return;
+		}
+	}
+#endif /* CONFIG_BITBANGMII */
+
 	ug_regs = ugeth->uec_mii_regs;
 
 	/* Stop the MII management read cycle */
@@ -140,6 +171,19 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
 	u32 tmp_reg;
 	u16 value;
 
+
+#if defined(CONFIG_BITBANGMII)
+	u32 i = 0;
+
+	for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+		if (strncmp(dev->name, bitbang_phy_port[i],
+			sizeof(dev->name)) == 0) {
+			(void)bb_miiphy_read(NULL, mii_id, regnum, &value);
+			return (value);
+		}
+	}
+#endif /* CONFIG_BITBANGMII */
+
 	ug_regs = ugeth->uec_mii_regs;
 
 	/* Setting up the MII Mangement Address Register */
@@ -195,7 +239,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info)
 	advertise = mii_info->advertising;
 
 	/* Setup standard advertisement */
-	adv = phy_read (mii_info, PHY_ANAR);
+	adv = uec_phy_read(mii_info, MII_ADVERTISE);
 	adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 	if (advertise & ADVERTISED_10baseT_Half)
 		adv |= ADVERTISE_10HALF;
@@ -205,7 +249,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info)
 		adv |= ADVERTISE_100HALF;
 	if (advertise & ADVERTISED_100baseT_Full)
 		adv |= ADVERTISE_100FULL;
-	phy_write (mii_info, PHY_ANAR, adv);
+	uec_phy_write(mii_info, MII_ADVERTISE, adv);
 }
 
 static void genmii_setup_forced (struct uec_mii_info *mii_info)
@@ -213,24 +257,24 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info)
 	u16 ctrl;
 	u32 features = mii_info->phyinfo->features;
 
-	ctrl = phy_read (mii_info, PHY_BMCR);
+	ctrl = uec_phy_read(mii_info, MII_BMCR);
 
-	ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
-		  PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
-	ctrl |= PHY_BMCR_RESET;
+	ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
+		  BMCR_SPEED1000 | BMCR_ANENABLE);
+	ctrl |= BMCR_RESET;
 
 	switch (mii_info->speed) {
 	case SPEED_1000:
 		if (features & (SUPPORTED_1000baseT_Half
 				| SUPPORTED_1000baseT_Full)) {
-			ctrl |= PHY_BMCR_1000_MBPS;
+			ctrl |= BMCR_SPEED1000;
 			break;
 		}
 		mii_info->speed = SPEED_100;
 	case SPEED_100:
 		if (features & (SUPPORTED_100baseT_Half
 				| SUPPORTED_100baseT_Full)) {
-			ctrl |= PHY_BMCR_100_MBPS;
+			ctrl |= BMCR_SPEED100;
 			break;
 		}
 		mii_info->speed = SPEED_10;
@@ -243,7 +287,7 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info)
 		break;
 	}
 
-	phy_write (mii_info, PHY_BMCR, ctrl);
+	uec_phy_write(mii_info, MII_BMCR, ctrl);
 }
 
 /* Enable and Restart Autonegotiation */
@@ -251,9 +295,9 @@ static void genmii_restart_aneg (struct uec_mii_info *mii_info)
 {
 	u16 ctl;
 
-	ctl = phy_read (mii_info, PHY_BMCR);
-	ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-	phy_write (mii_info, PHY_BMCR, ctl);
+	ctl = uec_phy_read(mii_info, MII_BMCR);
+	ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
+	uec_phy_write(mii_info, MII_BMCR, ctl);
 }
 
 static int gbit_config_aneg (struct uec_mii_info *mii_info)
@@ -266,14 +310,14 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info)
 		config_genmii_advert (mii_info);
 		advertise = mii_info->advertising;
 
-		adv = phy_read (mii_info, MII_1000BASETCONTROL);
-		adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
-			 MII_1000BASETCONTROL_HALFDUPLEXCAP);
+		adv = uec_phy_read(mii_info, MII_CTRL1000);
+		adv &= ~(ADVERTISE_1000FULL |
+			 ADVERTISE_1000HALF);
 		if (advertise & SUPPORTED_1000baseT_Half)
-			adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
+			adv |= ADVERTISE_1000HALF;
 		if (advertise & SUPPORTED_1000baseT_Full)
-			adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
-		phy_write (mii_info, MII_1000BASETCONTROL, adv);
+			adv |= ADVERTISE_1000FULL;
+		uec_phy_write(mii_info, MII_CTRL1000, adv);
 
 		/* Start/Restart aneg */
 		genmii_restart_aneg (mii_info);
@@ -288,13 +332,13 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info)
 	/* The Marvell PHY has an errata which requires
 	 * that certain registers get written in order
 	 * to restart autonegotiation */
-	phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
+	uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
 
-	phy_write (mii_info, 0x1d, 0x1f);
-	phy_write (mii_info, 0x1e, 0x200c);
-	phy_write (mii_info, 0x1d, 0x5);
-	phy_write (mii_info, 0x1e, 0);
-	phy_write (mii_info, 0x1e, 0x100);
+	uec_phy_write(mii_info, 0x1d, 0x1f);
+	uec_phy_write(mii_info, 0x1e, 0x200c);
+	uec_phy_write(mii_info, 0x1d, 0x5);
+	uec_phy_write(mii_info, 0x1e, 0);
+	uec_phy_write(mii_info, 0x1e, 0x100);
 
 	gbit_config_aneg (mii_info);
 
@@ -304,6 +348,15 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info)
 static int genmii_config_aneg (struct uec_mii_info *mii_info)
 {
 	if (mii_info->autoneg) {
+		/* Speed up the common case, if link is already up, speed and
+		   duplex match, skip auto neg as it already matches */
+		if (!genmii_read_status(mii_info) && mii_info->link)
+			if (mii_info->duplex == DUPLEX_FULL &&
+			    mii_info->speed == SPEED_100)
+				if (mii_info->advertising &
+				    ADVERTISED_100baseT_Full)
+					return 0;
+
 		config_genmii_advert (mii_info);
 		genmii_restart_aneg (mii_info);
 	} else
@@ -317,18 +370,18 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
 	u16 status;
 
 	/* Status is read once to clear old link state */
-	phy_read (mii_info, PHY_BMSR);
+	uec_phy_read(mii_info, MII_BMSR);
 
 	/*
 	 * Wait if the link is up, and autonegotiation is in progress
 	 * (ie - we're capable and it's not done)
 	 */
-	status = phy_read(mii_info, PHY_BMSR);
-	if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
-	    && !(status & PHY_BMSR_AUTN_COMP)) {
+	status = uec_phy_read(mii_info, MII_BMSR);
+	if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
+	    && !(status & BMSR_ANEGCOMPLETE)) {
 		int i = 0;
 
-		while (!(status & PHY_BMSR_AUTN_COMP)) {
+		while (!(status & BMSR_ANEGCOMPLETE)) {
 			/*
 			 * Timeout reached ?
 			 */
@@ -339,12 +392,11 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
 
 			i++;
 			udelay(1000);	/* 1 ms */
-			status = phy_read(mii_info, PHY_BMSR);
+			status = uec_phy_read(mii_info, MII_BMSR);
 		}
 		mii_info->link = 1;
-		udelay(500000);	/* another 500 ms (results in faster booting) */
 	} else {
-		if (status & PHY_BMSR_LS)
+		if (status & BMSR_LSTATUS)
 			mii_info->link = 1;
 		else
 			mii_info->link = 0;
@@ -365,7 +417,7 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
 		return err;
 
 	if (mii_info->autoneg) {
-		status = phy_read(mii_info, MII_1000BASETSTATUS);
+		status = uec_phy_read(mii_info, MII_STAT1000);
 
 		if (status & (LPA_1000FULL | LPA_1000HALF)) {
 			mii_info->speed = SPEED_1000;
@@ -374,13 +426,13 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
 			else
 				mii_info->duplex = DUPLEX_HALF;
 		} else {
-			status = phy_read(mii_info, PHY_ANLPAR);
+			status = uec_phy_read(mii_info, MII_LPA);
 
-			if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+			if (status & (LPA_10FULL | LPA_100FULL))
 				mii_info->duplex = DUPLEX_FULL;
 			else
 				mii_info->duplex = DUPLEX_HALF;
-			if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+			if (status & (LPA_100FULL | LPA_100HALF))
 				mii_info->speed = SPEED_100;
 			else
 				mii_info->speed = SPEED_10;
@@ -401,62 +453,63 @@ static int bcm_init(struct uec_mii_info *mii_info)
 
 	gbit_config_aneg(mii_info);
 
-	if ((uec->uec_info->enet_interface_type == RGMII_RXID) &&
-	   (uec->uec_info->speed == 1000)) {
+	if ((uec->uec_info->enet_interface_type ==
+				PHY_INTERFACE_MODE_RGMII_RXID) &&
+			(uec->uec_info->speed == SPEED_1000)) {
 		u16 val;
 		int cnt = 50;
 
 		/* Wait for aneg to complete. */
 		do
-			val = phy_read(mii_info, PHY_BMSR);
-		while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
+			val = uec_phy_read(mii_info, MII_BMSR);
+		while (--cnt && !(val & BMSR_ANEGCOMPLETE));
 
 		/* Set RDX clk delay. */
-		phy_write(mii_info, 0x18, 0x7 | (7 << 12));
+		uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
 
-		val = phy_read(mii_info, 0x18);
+		val = uec_phy_read(mii_info, 0x18);
 		/* Set RDX-RXC skew. */
 		val |= (1 << 8);
 		val |= (7 | (7 << 12));
 		/* Write bits 14:0. */
 		val |= (1 << 15);
-		phy_write(mii_info, 0x18, val);
+		uec_phy_write(mii_info, 0x18, val);
 	}
 
 	 return 0;
 }
 
-static int marvell_init(struct uec_mii_info *mii_info)
+static int uec_marvell_init(struct uec_mii_info *mii_info)
 {
 	struct eth_device *edev = mii_info->dev;
 	uec_private_t *uec = edev->priv;
-	enum enet_interface_type iface = uec->uec_info->enet_interface_type;
+	phy_interface_t iface = uec->uec_info->enet_interface_type;
 	int	speed = uec->uec_info->speed;
 
-	if ((speed == 1000) &&
-	   (iface == RGMII_ID ||
-	    iface == RGMII_RXID ||
-	    iface == RGMII_TXID)) {
+	if ((speed == SPEED_1000) &&
+	   (iface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    iface == PHY_INTERFACE_MODE_RGMII_RXID ||
+	    iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 		int temp;
 
-		temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
-		if (iface == RGMII_ID) {
+		temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
+		if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
 			temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
-		} else if (iface == RGMII_RXID) {
+		} else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
 			temp &= ~MII_M1111_TX_DELAY;
 			temp |= MII_M1111_RX_DELAY;
-		} else if (iface == RGMII_TXID) {
+		} else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
 			temp &= ~MII_M1111_RX_DELAY;
 			temp |= MII_M1111_TX_DELAY;
 		}
-		phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
+		uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
 
-		temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
+		temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
 		temp &= ~MII_M1111_HWCFG_MODE_MASK;
 		temp |= MII_M1111_HWCFG_MODE_RGMII;
-		phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
+		uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
 
-		phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
+		uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
 	}
 
 	return 0;
@@ -479,7 +532,7 @@ static int marvell_read_status (struct uec_mii_info *mii_info)
 	if (mii_info->autoneg && mii_info->link) {
 		int speed;
 
-		status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
+		status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
 
 		/* Get the duplexity */
 		if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
@@ -509,7 +562,7 @@ static int marvell_read_status (struct uec_mii_info *mii_info)
 static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
 {
 	/* Clear the interrupts by reading the reg */
-	phy_read (mii_info, MII_M1011_IEVENT);
+	uec_phy_read(mii_info, MII_M1011_IEVENT);
 
 	return 0;
 }
@@ -517,9 +570,10 @@ static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
 static int marvell_config_intr (struct uec_mii_info *mii_info)
 {
 	if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
-		phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
+		uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 	else
-		phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
+		uec_phy_write(mii_info, MII_M1011_IMASK,
+				MII_M1011_IMASK_CLEAR);
 
 	return 0;
 }
@@ -527,13 +581,13 @@ static int marvell_config_intr (struct uec_mii_info *mii_info)
 static int dm9161_init (struct uec_mii_info *mii_info)
 {
 	/* Reset the PHY */
-	phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
-		   PHY_BMCR_RESET);
+	uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
+		   BMCR_RESET);
 	/* PHY and MAC connect */
-	phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
-		   ~PHY_BMCR_ISO);
+	uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
+		   ~BMCR_ISOLATE);
 
-	phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
+	uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
 
 	config_genmii_advert (mii_info);
 	/* Start/restart aneg */
@@ -559,7 +613,7 @@ static int dm9161_read_status (struct uec_mii_info *mii_info)
 	/* If the link is up, read the speed and duplex
 	   If we aren't autonegotiating assume speeds are as set */
 	if (mii_info->autoneg && mii_info->link) {
-		status = phy_read (mii_info, MII_DM9161_SCSR);
+		status = uec_phy_read(mii_info, MII_DM9161_SCSR);
 		if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
 			mii_info->speed = SPEED_100;
 		else
@@ -577,7 +631,7 @@ static int dm9161_read_status (struct uec_mii_info *mii_info)
 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
 {
 	/* Clear the interrupt by reading the reg */
-	phy_read (mii_info, MII_DM9161_INTR);
+	uec_phy_read(mii_info, MII_DM9161_INTR);
 
 	return 0;
 }
@@ -585,9 +639,9 @@ static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
 static int dm9161_config_intr (struct uec_mii_info *mii_info)
 {
 	if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
-		phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
+		uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
 	else
-		phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
+		uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
 
 	return 0;
 }
@@ -641,7 +695,7 @@ static int smsc_read_status (struct uec_mii_info *mii_info)
 	if (mii_info->autoneg && mii_info->link) {
 		int	val;
 
-		status = phy_read (mii_info, 0x1f);
+		status = uec_phy_read(mii_info, 0x1f);
 		val = (status & 0x1c) >> 2;
 
 		switch (val) {
@@ -696,7 +750,7 @@ static struct phy_info phy_info_marvell = {
 	.phy_id_mask = 0xffffff00,
 	.name = "Marvell 88E11x1",
 	.features = MII_GBIT_FEATURES,
-	.init = &marvell_init,
+	.init = &uec_marvell_init,
 	.config_aneg = &marvell_config_aneg,
 	.read_status = &marvell_read_status,
 	.ack_interrupt = &marvell_ack_interrupt,
@@ -749,12 +803,12 @@ static struct phy_info *phy_info[] = {
 	NULL
 };
 
-u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
+u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
 {
 	return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
 }
 
-void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
+void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
 {
 	mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
 }
@@ -770,11 +824,11 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
 	struct phy_info *theInfo = NULL;
 
 	/* Grab the bits from PHYIR1, and put them in the upper half */
-	phy_reg = phy_read (mii_info, PHY_PHYIDR1);
+	phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
 	phy_ID = (phy_reg & 0xffff) << 16;
 
 	/* Grab the bits from PHYIR2, and put them in the lower half */
-	phy_reg = phy_read (mii_info, PHY_PHYIDR2);
+	phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
 	phy_ID |= (phy_reg & 0xffff);
 
 	/* loop through all the known PHY types, and find one that */
@@ -797,10 +851,8 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
 	return theInfo;
 }
 
-void marvell_phy_interface_mode (struct eth_device *dev,
-				 enet_interface_type_e type,
-				 int speed
-				)
+void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
+		int speed)
 {
 	uec_private_t *uec = (uec_private_t *) dev->priv;
 	struct uec_mii_info *mii_info;
@@ -812,47 +864,47 @@ void marvell_phy_interface_mode (struct eth_device *dev,
 	}
 	mii_info = uec->mii_info;
 
-	if (type == RGMII) {
-		if (speed == 100) {
-			phy_write (mii_info, 0x00, 0x9140);
-			phy_write (mii_info, 0x1d, 0x001f);
-			phy_write (mii_info, 0x1e, 0x200c);
-			phy_write (mii_info, 0x1d, 0x0005);
-			phy_write (mii_info, 0x1e, 0x0000);
-			phy_write (mii_info, 0x1e, 0x0100);
-			phy_write (mii_info, 0x09, 0x0e00);
-			phy_write (mii_info, 0x04, 0x01e1);
-			phy_write (mii_info, 0x00, 0x9140);
-			phy_write (mii_info, 0x00, 0x1000);
-			udelay (100000);
-			phy_write (mii_info, 0x00, 0x2900);
-			phy_write (mii_info, 0x14, 0x0cd2);
-			phy_write (mii_info, 0x00, 0xa100);
-			phy_write (mii_info, 0x09, 0x0000);
-			phy_write (mii_info, 0x1b, 0x800b);
-			phy_write (mii_info, 0x04, 0x05e1);
-			phy_write (mii_info, 0x00, 0xa100);
-			phy_write (mii_info, 0x00, 0x2100);
-			udelay (1000000);
-		} else if (speed == 10) {
-			phy_write (mii_info, 0x14, 0x8e40);
-			phy_write (mii_info, 0x1b, 0x800b);
-			phy_write (mii_info, 0x14, 0x0c82);
-			phy_write (mii_info, 0x00, 0x8100);
-			udelay (1000000);
+	if (type == PHY_INTERFACE_MODE_RGMII) {
+		if (speed == SPEED_100) {
+			uec_phy_write(mii_info, 0x00, 0x9140);
+			uec_phy_write(mii_info, 0x1d, 0x001f);
+			uec_phy_write(mii_info, 0x1e, 0x200c);
+			uec_phy_write(mii_info, 0x1d, 0x0005);
+			uec_phy_write(mii_info, 0x1e, 0x0000);
+			uec_phy_write(mii_info, 0x1e, 0x0100);
+			uec_phy_write(mii_info, 0x09, 0x0e00);
+			uec_phy_write(mii_info, 0x04, 0x01e1);
+			uec_phy_write(mii_info, 0x00, 0x9140);
+			uec_phy_write(mii_info, 0x00, 0x1000);
+			mdelay(100);
+			uec_phy_write(mii_info, 0x00, 0x2900);
+			uec_phy_write(mii_info, 0x14, 0x0cd2);
+			uec_phy_write(mii_info, 0x00, 0xa100);
+			uec_phy_write(mii_info, 0x09, 0x0000);
+			uec_phy_write(mii_info, 0x1b, 0x800b);
+			uec_phy_write(mii_info, 0x04, 0x05e1);
+			uec_phy_write(mii_info, 0x00, 0xa100);
+			uec_phy_write(mii_info, 0x00, 0x2100);
+			mdelay(1000);
+		} else if (speed == SPEED_10) {
+			uec_phy_write(mii_info, 0x14, 0x8e40);
+			uec_phy_write(mii_info, 0x1b, 0x800b);
+			uec_phy_write(mii_info, 0x14, 0x0c82);
+			uec_phy_write(mii_info, 0x00, 0x8100);
+			mdelay(1000);
 		}
 	}
 
 	/* handle 88e1111 rev.B2 erratum 5.6 */
 	if (mii_info->autoneg) {
-		status = phy_read (mii_info, PHY_BMCR);
-		phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
+		status = uec_phy_read(mii_info, MII_BMCR);
+		uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
 	}
 	/* now the B2 will correctly report autoneg completion status */
 }
 
 void change_phy_interface_mode (struct eth_device *dev,
-				enet_interface_type_e type, int speed)
+				phy_interface_t type, int speed)
 {
 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
 	marvell_phy_interface_mode (dev, type, speed);