X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fqe%2Fuec.c;h=b3af707a3d0b6304f1c8f8cfe954d62957868ee4;hb=7c839ea70c4991e8d4c322e074359ac5e155d59d;hp=468c92ebced50feb0c991824a404b72fc6f93afb;hpb=0fcb9f07a1d086fc6951c08d2fc1cf6048bd54e2;p=oweals%2Fu-boot.git diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 468c92ebce..b3af707a3d 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -6,12 +6,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "common.h" -#include "net.h" -#include "malloc.h" -#include "asm/errno.h" -#include "asm/io.h" -#include "linux/immap_qe.h" +#include +#include +#include +#include +#include +#include #include "uccf.h" #include "uec.h" #include "uec_phy.h" @@ -567,7 +567,7 @@ static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* QE9 and QE12 need to be set for enabling QE MII managment signals */ @@ -578,7 +578,7 @@ static void phy_change(struct eth_device *dev) /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* * QE12 is muxed with LBCTL, it needs to be released for enabling * LBCTL signal for LBC usage. @@ -1193,14 +1193,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd) uec_private_t *uec; int err, i; struct phy_info *curphy; -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif uec = (uec_private_t *)dev->priv; if (uec->the_first_run == 0) { -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE9 and QE12 need to be set for enabling QE MII managment signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); @@ -1232,7 +1232,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd) udelay(100000); } while (1); -#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) +#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) /* QE12 needs to be released for enabling LBCTL signal*/ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif