X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fphy%2Fmarvell%2Fcomphy_a3700.c;h=dc188c44e0d63351f6bb6d90097288f8462515d1;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=3da9eedc231c1cbd4fd09ad4d8b890d2cfdb02f9;hpb=de49bd0e73f7d4e764f3c6b67a536de5d4e8841b;p=oweals%2Fu-boot.git

diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 3da9eedc23..dc188c44e0 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -5,14 +5,48 @@
 
 #include <common.h>
 #include <fdtdec.h>
+#include <log.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
+#include <linux/delay.h>
 
 #include "comphy_a3700.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct comphy_mux_data a3700_comphy_mux_data[] = {
+/* Lane 0 */
+	{
+		4,
+		{
+			{ PHY_TYPE_UNCONNECTED,	0x0 },
+			{ PHY_TYPE_SGMII1,	0x0 },
+			{ PHY_TYPE_USB3_HOST0,	0x1 },
+			{ PHY_TYPE_USB3_DEVICE,	0x1 }
+		}
+	},
+/* Lane 1 */
+	{
+		3,
+		{
+			{ PHY_TYPE_UNCONNECTED,	0x0},
+			{ PHY_TYPE_SGMII0,	0x0},
+			{ PHY_TYPE_PEX0,	0x1}
+		}
+	},
+/* Lane 2 */
+	{
+		4,
+		{
+			{ PHY_TYPE_UNCONNECTED,	0x0},
+			{ PHY_TYPE_SATA0,	0x0},
+			{ PHY_TYPE_USB3_HOST0,	0x1},
+			{ PHY_TYPE_USB3_DEVICE,	0x1}
+		}
+	},
+};
+
 struct sgmii_phy_init_data_fix {
 	u16 addr;
 	u16 value;
@@ -349,13 +383,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
 	usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane);
 
 	/*
-	 * unset BIT0: set Tx Electrical Idle Mode: Transmitter is in
-	 *             low impedance mode during electrical idle
-	 * unset BIT4: set G2 Tx Datapath with no Delayed Latency
-	 * unset BIT6: set Tx Detect Rx Mode at LoZ mode
+	 * Set BIT0: enable transmitter in high impedance mode
+	 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
+	 * Set BIT6: Tx detect Rx at HiZ mode
+	 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
+	 *              together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR
+	 *              register
 	 */
-	usb3_reg_set16(LANE_CFG1, 0x0, 0xFFFF, lane);
-
+	usb3_reg_set16(LANE_CFG1,
+		       tx_det_rx_mode | gen2_tx_data_dly_deft
+		       | tx_elec_idle_mode_en,
+		       prd_txdeemph1_mask | tx_det_rx_mode
+		       | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane);
 
 	/* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
 	usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane);
@@ -425,7 +464,17 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
 		usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
 
 	/*
-	 * 10. Release SW reset
+	 * 10. Set max speed generation to USB3.0 5Gbps
+	 */
+	usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane);
+
+	/*
+	 * 11. Set capacitor value for FFE gain peaking to 0xF
+	 */
+	usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane);
+
+	/*
+	 * 12. Release SW reset
 	 */
 	usb3_reg_set16(GLOB_PHY_CTRL0,
 		       rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
@@ -650,13 +699,15 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed)
 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
 {
 	int ret;
+	u32 saved_selector;
 
 	debug_enter();
 
 	/*
 	 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
 	 */
-	reg_set(COMPHY_SEL_ADDR, 0, rf_compy_select(lane));
+	saved_selector = readl(COMPHY_SEL_ADDR);
+	reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF);
 
 	/*
 	 * 2. Reset PHY by setting PHY input port PIN_RESET=1.
@@ -827,6 +878,11 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
 	if (!ret)
 		printf("Failed to init RX of SGMII PHY %d\n", lane);
 
+	/*
+	 * Restore saved selector.
+	 */
+	reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
+
 	debug_exit();
 
 	return ret;
@@ -846,7 +902,7 @@ void comphy_dedicated_phys_init(void)
 		 */
 		if (usb32 == 0) {
 			node = fdt_node_offset_by_compatible(
-				blob, -1, "marvell,armada-3700-ehci");
+				blob, -1, "marvell,armada3700-ehci");
 		} else {
 			node = fdt_node_offset_by_compatible(
 				blob, -1, "marvell,armada3700-xhci");
@@ -917,6 +973,10 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
 
 	debug_enter();
 
+	/* Initialize PHY mux */
+	chip_cfg->mux_data = a3700_comphy_mux_data;
+	comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR);
+
 	for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
 	     lane++, comphy_map++) {
 		debug("Initialize serdes number %d\n", lane);