X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fzynq_gem.c;h=6dd87cf28f95540da795f9b414be4def7e494439;hb=0ea38db90caa55e8366c9bef4214ab52b3fedf6a;hp=eac9b6f4584466e56d1b9646fb7ff9bae88e53ed;hpb=f97d7e8be96888b622309d9563da0ab3fba0534b;p=oweals%2Fu-boot.git diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index eac9b6f458..6dd87cf28f 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -6,39 +6,28 @@ * Based on Xilinx gmac driver: * (C) Copyright 2011 Xilinx * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ +#include #include +#include #include +#include #include +#include #include #include #include #include +#include #include +#include #include #include +#include -#if !defined(CONFIG_PHYLIB) -# error XILINX_GEM_ETHERNET requires PHYLIB -#endif +DECLARE_GLOBAL_DATA_PTR; /* Bit/mask specification */ #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ @@ -58,25 +47,33 @@ /* Wrap bit, last descriptor */ #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ - -#define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */ -#define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */ -/* Transmit buffs exhausted mid frame */ -#define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010 +#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ -#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ -#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ -#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ -#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ -#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ +#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ +#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ +#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ +#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ +#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ +#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ +#ifdef CONFIG_ARM64 +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ +#else +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ +#endif + +#ifdef CONFIG_ARM64 +# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ +#else +# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ +#endif -#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \ +#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ + ZYNQ_GEM_NWCFG_FDEN | \ ZYNQ_GEM_NWCFG_FSREM | \ ZYNQ_GEM_NWCFG_MDCCLKDIV) @@ -95,6 +92,10 @@ ZYNQ_GEM_DMACR_TXSIZE | \ ZYNQ_GEM_DMACR_RXBUF) +#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ + +#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -106,30 +107,47 @@ */ #define PHY_DETECT_MASK 0x1808 +/* TX BD status masks */ +#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff +#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 +#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 + +/* Clock frequencies for different speeds */ +#define ZYNQ_GEM_FREQUENCY_10 2500000UL +#define ZYNQ_GEM_FREQUENCY_100 25000000UL +#define ZYNQ_GEM_FREQUENCY_1000 125000000UL + /* Device registers */ struct zynq_gem_regs { - u32 nwctrl; /* Network Control reg */ - u32 nwcfg; /* Network Config reg */ - u32 nwsr; /* Network Status reg */ + u32 nwctrl; /* 0x0 - Network Control reg */ + u32 nwcfg; /* 0x4 - Network Config reg */ + u32 nwsr; /* 0x8 - Network Status reg */ u32 reserved1; - u32 dmacr; /* DMA Control reg */ - u32 txsr; /* TX Status reg */ - u32 rxqbase; /* RX Q Base address reg */ - u32 txqbase; /* TX Q Base address reg */ - u32 rxsr; /* RX Status reg */ + u32 dmacr; /* 0x10 - DMA Control reg */ + u32 txsr; /* 0x14 - TX Status reg */ + u32 rxqbase; /* 0x18 - RX Q Base address reg */ + u32 txqbase; /* 0x1c - TX Q Base address reg */ + u32 rxsr; /* 0x20 - RX Status reg */ u32 reserved2[2]; - u32 idr; /* Interrupt Disable reg */ + u32 idr; /* 0x2c - Interrupt Disable reg */ u32 reserved3; - u32 phymntnc; /* Phy Maintaince reg */ + u32 phymntnc; /* 0x34 - Phy Maintaince reg */ u32 reserved4[18]; - u32 hashl; /* Hash Low address reg */ - u32 hashh; /* Hash High address reg */ + u32 hashl; /* 0x80 - Hash Low address reg */ + u32 hashh; /* 0x84 - Hash High address reg */ #define LADDR_LOW 0 #define LADDR_HIGH 1 - u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */ - u32 match[4]; /* Type ID1 Match reg */ + u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ + u32 match[4]; /* 0xa8 - Type ID1 Match reg */ u32 reserved6[18]; - u32 stat[44]; /* Octects transmitted Low reg - stat start */ +#define STAT_SIZE 44 + u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ + u32 reserved9[20]; + u32 pcscntrl; + u32 reserved7[143]; + u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ + u32 reserved8[15]; + u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ }; /* BD descriptors */ @@ -138,50 +156,48 @@ struct emac_bd { u32 status; }; -#define RX_BUF 3 +#define RX_BUF 32 +/* Page table entries are set to 1MB, or multiples of 1MB + * (not < 1MB). driver uses less bd's so use 1MB bdspace. + */ +#define BD_SPACE 0x100000 +/* BD separation space */ +#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) + +/* Setup the first free TX descriptor */ +#define TX_FREE_DESC 2 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ struct zynq_gem_priv { - struct emac_bd tx_bd; - struct emac_bd rx_bd[RX_BUF]; - char rxbuffers[RX_BUF * PKTSIZE_ALIGN]; + struct emac_bd *tx_bd; + struct emac_bd *rx_bd; + char *rxbuffers; u32 rxbd_current; u32 rx_first_buf; int phyaddr; u32 emio; int init; + struct zynq_gem_regs *iobase; + phy_interface_t interface; struct phy_device *phydev; + int phy_of_handle; struct mii_dev *bus; +#ifdef CONFIG_CLK_ZYNQMP + struct clk clk; +#endif }; -static inline int mdio_wait(struct eth_device *dev) -{ - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - u32 timeout = 200; - - /* Wait till MDIO interface is ready to accept a new transaction. */ - while (--timeout) { - if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) - break; - WATCHDOG_RESET(); - } - - if (!timeout) { - printf("%s: Timeout\n", __func__); - return 1; - } - - return 0; -} - -static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, - u32 op, u16 *data) +static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, + u32 op, u16 *data) { u32 mgtcr; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_regs *regs = priv->iobase; + int err; - if (mdio_wait(dev)) - return 1; + err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, + true, 20000, true); + if (err) + return err; /* Construct mgtcr mask for the operation */ mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | @@ -191,8 +207,10 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, /* Write mgtcr and wait for completion */ writel(mgtcr, ®s->phymntnc); - if (mdio_wait(dev)) - return 1; + err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, + true, 20000, true); + if (err) + return err; if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) *data = readl(®s->phymntnc); @@ -200,32 +218,45 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum, return 0; } -static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val) +static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr, + u32 regnum, u16 *val) { - return phy_setup_op(dev, phy_addr, regnum, - ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); + u32 ret; + + ret = phy_setup_op(priv, phy_addr, regnum, + ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); + + if (!ret) + debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, + phy_addr, regnum, *val); + + return ret; } -static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data) +static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr, + u32 regnum, u16 data) { - return phy_setup_op(dev, phy_addr, regnum, - ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); + debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, + regnum, data); + + return phy_setup_op(priv, phy_addr, regnum, + ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); } -static void phy_detection(struct eth_device *dev) +static int phy_detection(struct udevice *dev) { int i; u16 phyreg; struct zynq_gem_priv *priv = dev->priv; if (priv->phyaddr != -1) { - phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg); + phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ debug("Default phy address %d is valid\n", priv->phyaddr); - return; + return 0; } else { debug("PHY address is not setup correctly %d\n", priv->phyaddr); @@ -237,33 +268,36 @@ static void phy_detection(struct eth_device *dev) if (priv->phyaddr == -1) { /* detect the PHY address */ for (i = 31; i >= 0; i--) { - phyread(dev, i, PHY_DETECT_REG, &phyreg); + phyread(priv, i, PHY_DETECT_REG, &phyreg); if ((phyreg != 0xFFFF) && ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { /* Found a valid PHY address */ priv->phyaddr = i; debug("Found valid phy address, %d\n", i); - return; + return 0; } } } printf("PHY is not detected\n"); + return -1; } -static int zynq_gem_setup_mac(struct eth_device *dev) +static int zynq_gem_setup_mac(struct udevice *dev) { u32 i, macaddrlow, macaddrhigh; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; /* Set the MAC bits [31:0] in BOT */ - macaddrlow = dev->enetaddr[0]; - macaddrlow |= dev->enetaddr[1] << 8; - macaddrlow |= dev->enetaddr[2] << 16; - macaddrlow |= dev->enetaddr[3] << 24; + macaddrlow = pdata->enetaddr[0]; + macaddrlow |= pdata->enetaddr[1] << 8; + macaddrlow |= pdata->enetaddr[2] << 16; + macaddrlow |= pdata->enetaddr[3] << 24; /* Set MAC bits [47:32] in TOP */ - macaddrhigh = dev->enetaddr[4]; - macaddrhigh |= dev->enetaddr[5] << 8; + macaddrhigh = pdata->enetaddr[4]; + macaddrhigh |= pdata->enetaddr[5] << 8; for (i = 0; i < 4; i++) { writel(0, ®s->laddr[i][LADDR_LOW]); @@ -278,14 +312,11 @@ static int zynq_gem_setup_mac(struct eth_device *dev) return 0; } -static int zynq_gem_init(struct eth_device *dev, bd_t * bis) +static int zynq_phy_init(struct udevice *dev) { - u32 i, rclk, clk = 0; - struct phy_device *phydev; - const u32 stat_size = (sizeof(struct zynq_gem_regs) - - offsetof(struct zynq_gem_regs, stat)) / 4; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - struct zynq_gem_priv *priv = dev->priv; + int ret; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -293,6 +324,42 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full; + /* Enable only MDIO bus */ + writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); + + if (priv->interface != PHY_INTERFACE_MODE_SGMII) { + ret = phy_detection(dev); + if (ret) { + printf("GEM PHY init failed\n"); + return ret; + } + } + + priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, + priv->interface); + if (!priv->phydev) + return -ENODEV; + + priv->phydev->supported = supported | ADVERTISED_Pause | + ADVERTISED_Asym_Pause; + priv->phydev->advertising = priv->phydev->supported; + + if (priv->phy_of_handle > 0) + priv->phydev->dev->of_offset = priv->phy_of_handle; + + return phy_config(priv->phydev); +} + +static int zynq_gem_init(struct udevice *dev) +{ + u32 i, nwconfig; + int ret; + unsigned long clk_rate = 0; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; + struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; + if (!priv->init) { /* Disable all interrupts */ writel(0xFFFFFFFF, ®s->idr); @@ -311,24 +378,22 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) writel(0x0, ®s->hashh); /* Clear all counters */ - for (i = 0; i <= stat_size; i++) + for (i = 0; i < STAT_SIZE; i++) readl(®s->stat[i]); /* Setup RxBD space */ - memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd)); - /* Create the RxBD ring */ - memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers)); + memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); for (i = 0; i < RX_BUF; i++) { priv->rx_bd[i].status = 0xF0000000; priv->rx_bd[i].addr = - (u32)((char *)&(priv->rxbuffers) + + ((ulong)(priv->rxbuffers) + (i * PKTSIZE_ALIGN)); } /* WRAP bit to last BD */ priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; /* Write RxBDs to IP */ - writel((u32)&(priv->rx_bd), ®s->rxqbase); + writel((ulong)priv->rx_bd, ®s->rxqbase); /* Setup for DMA Configuration register */ writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); @@ -336,45 +401,72 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) /* Setup for Network Control register, MDIO, Rx and Tx enable */ setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); + /* Disable the second priority queue */ + dummy_tx_bd->addr = 0; + dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | + ZYNQ_GEM_TXBUF_LAST_MASK| + ZYNQ_GEM_TXBUF_USED_MASK; + + dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | + ZYNQ_GEM_RXBUF_NEW_MASK; + dummy_rx_bd->status = 0; + flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + + sizeof(dummy_tx_bd)); + flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + + sizeof(dummy_rx_bd)); + + writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); + writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); + priv->init++; } - phy_detection(dev); + ret = phy_startup(priv->phydev); + if (ret) + return ret; + + if (!priv->phydev->link) { + printf("%s: No link.\n", priv->phydev->dev->name); + return -1; + } - /* interface - look at tsec */ - phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0); + nwconfig = ZYNQ_GEM_NWCFG_INIT; - phydev->supported = supported | ADVERTISED_Pause | - ADVERTISED_Asym_Pause; - phydev->advertising = phydev->supported; - priv->phydev = phydev; - phy_config(phydev); - phy_startup(phydev); + if (priv->interface == PHY_INTERFACE_MODE_SGMII) { + nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | + ZYNQ_GEM_NWCFG_PCS_SEL; +#ifdef CONFIG_ARM64 + writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, + ®s->pcscntrl); +#endif + } - switch (phydev->speed) { + switch (priv->phydev->speed) { case SPEED_1000: - writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); - rclk = (0 << 4) | (1 << 0); - clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: - clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, - ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); - rclk = 1 << 0; - clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, + ®s->nwcfg); + clk_rate = ZYNQ_GEM_FREQUENCY_100; break; case SPEED_10: - rclk = 1 << 0; - /* FIXME untested */ - clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_10; break; } /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) - zynq_slcr_gem_clk_setup(dev->iobase != - ZYNQ_GEM_BASEADDR0, rclk, clk); +#ifndef CONFIG_CLK_ZYNQMP + zynq_slcr_gem_clk_setup((ulong)priv->iobase != + ZYNQ_GEM_BASEADDR0, clk_rate); +#else + ret = clk_set_rate(&priv->clk, clk_rate); + if (IS_ERR_VALUE(ret)) + return -1; +#endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); @@ -382,140 +474,262 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) return 0; } -static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) +static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { - u32 status; - struct zynq_gem_priv *priv = dev->priv; - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \ - ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK; + u32 addr, size; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; + struct emac_bd *current_bd = &priv->tx_bd[1]; + + /* Setup Tx BD */ + memset(priv->tx_bd, 0, sizeof(struct emac_bd)); + + priv->tx_bd->addr = (ulong)ptr; + priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | + ZYNQ_GEM_TXBUF_LAST_MASK; + /* Dummy descriptor to mark it as the last in descriptor chain */ + current_bd->addr = 0x0; + current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | + ZYNQ_GEM_TXBUF_LAST_MASK| + ZYNQ_GEM_TXBUF_USED_MASK; /* setup BD */ - writel((u32)&(priv->tx_bd), ®s->txqbase); + writel((ulong)priv->tx_bd, ®s->txqbase); - /* Setup Tx BD */ - memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd)); + addr = (ulong) ptr; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup(len, ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); - priv->tx_bd.addr = (u32)ptr; - priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK; + addr = (ulong)priv->rxbuffers; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); + barrier(); /* Start transmit */ setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); - /* Read the stat register to know if the packet has been transmitted */ - status = readl(®s->txsr); - if (status & mask) - printf("Something has gone wrong here!? Status is 0x%x.\n", - status); + /* Read TX BD status */ + if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) + printf("TX buffers exhausted in mid frame\n"); - /* Clear Tx status register before leaving . */ - writel(status, ®s->txsr); - return 0; + return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, + true, 20000, true); } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ -static int zynq_gem_recv(struct eth_device *dev) +static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) { int frame_len; - struct zynq_gem_priv *priv = dev->priv; + u32 addr; + struct zynq_gem_priv *priv = dev_get_priv(dev); struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; - struct emac_bd *first_bd; if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) - return 0; + return -1; if (!(current_bd->status & (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { printf("GEM: SOF or EOF not set for last buffer received!\n"); - return 0; + return -1; } frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; - if (frame_len) { - NetReceive((u8 *) (current_bd->addr & - ZYNQ_GEM_RXBUF_ADD_MASK), frame_len); - - if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) - priv->rx_first_buf = priv->rxbd_current; - else { - current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; - current_bd->status = 0xF0000000; /* FIXME */ - } + if (!frame_len) { + printf("%s: Zero size packet?\n", __func__); + return -1; + } - if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { - first_bd = &priv->rx_bd[priv->rx_first_buf]; - first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; - first_bd->status = 0xF0000000; - } + addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; + addr &= ~(ARCH_DMA_MINALIGN - 1); + *packetp = (uchar *)(uintptr_t)addr; + + return frame_len; +} - if ((++priv->rxbd_current) >= RX_BUF) - priv->rxbd_current = 0; +static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; + struct emac_bd *first_bd; + + if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { + priv->rx_first_buf = priv->rxbd_current; + } else { + current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + current_bd->status = 0xF0000000; /* FIXME */ } - return frame_len; + if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { + first_bd = &priv->rx_bd[priv->rx_first_buf]; + first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; + first_bd->status = 0xF0000000; + } + + if ((++priv->rxbd_current) >= RX_BUF) + priv->rxbd_current = 0; + + return 0; } -static void zynq_gem_halt(struct eth_device *dev) +static void zynq_gem_halt(struct udevice *dev) { - struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; + struct zynq_gem_priv *priv = dev_get_priv(dev); + struct zynq_gem_regs *regs = priv->iobase; clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } -static int zynq_gem_miiphyread(const char *devname, uchar addr, - uchar reg, ushort *val) +__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) { - struct eth_device *dev = eth_get_dev(); + return -ENOSYS; +} + +static int zynq_gem_read_rom_mac(struct udevice *dev) +{ + int retval; + struct eth_pdata *pdata = dev_get_platdata(dev); + + retval = zynq_board_read_rom_ethaddr(pdata->enetaddr); + if (retval == -ENOSYS) + retval = 0; + + return retval; +} + +static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, + int devad, int reg) +{ + struct zynq_gem_priv *priv = bus->priv; int ret; + u16 val; - ret = phyread(dev, addr, reg, val); - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val); - return ret; + ret = phyread(priv, addr, reg, &val); + debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); + return val; } -static int zynq_gem_miiphy_write(const char *devname, uchar addr, - uchar reg, ushort val) +static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { - struct eth_device *dev = eth_get_dev(); + struct zynq_gem_priv *priv = bus->priv; - debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val); - return phywrite(dev, addr, reg, val); + debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); + return phywrite(priv, addr, reg, value); } -int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) +static int zynq_gem_probe(struct udevice *dev) { - struct eth_device *dev; - struct zynq_gem_priv *priv; + void *bd_space; + struct zynq_gem_priv *priv = dev_get_priv(dev); + int ret; - dev = calloc(1, sizeof(*dev)); - if (dev == NULL) - return -1; + /* Align rxbuffers to ARCH_DMA_MINALIGN */ + priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); + memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); - dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); - if (dev->priv == NULL) { - free(dev); - return -1; + /* Align bd_space to MMU_SECTION_SHIFT */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, + BD_SPACE, DCACHE_OFF); + + /* Initialize the bd spaces for tx and rx bd's */ + priv->tx_bd = (struct emac_bd *)bd_space; + priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); + +#ifdef CONFIG_CLK_ZYNQMP + ret = clk_get_by_name(dev, "tx_clk", &priv->clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return -EINVAL; } - priv = dev->priv; +#endif - priv->phyaddr = phy_addr; - priv->emio = emio; + priv->bus = mdio_alloc(); + priv->bus->read = zynq_gem_miiphy_read; + priv->bus->write = zynq_gem_miiphy_write; + priv->bus->priv = priv; - sprintf(dev->name, "Gem.%x", base_addr); + ret = mdio_register_seq(priv->bus, dev->seq); + if (ret) + return ret; - dev->iobase = base_addr; + return zynq_phy_init(dev); +} - dev->init = zynq_gem_init; - dev->halt = zynq_gem_halt; - dev->send = zynq_gem_send; - dev->recv = zynq_gem_recv; - dev->write_hwaddr = zynq_gem_setup_mac; +static int zynq_gem_remove(struct udevice *dev) +{ + struct zynq_gem_priv *priv = dev_get_priv(dev); - eth_register(dev); + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); - miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); - priv->bus = miiphy_get_dev_by_name(dev->name); + return 0; +} + +static const struct eth_ops zynq_gem_ops = { + .start = zynq_gem_init, + .send = zynq_gem_send, + .recv = zynq_gem_recv, + .free_pkt = zynq_gem_free_pkt, + .stop = zynq_gem_halt, + .write_hwaddr = zynq_gem_setup_mac, + .read_rom_hwaddr = zynq_gem_read_rom_mac, +}; + +static int zynq_gem_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct zynq_gem_priv *priv = dev_get_priv(dev); + const char *phy_mode; + + pdata->iobase = (phys_addr_t)dev_get_addr(dev); + priv->iobase = (struct zynq_gem_regs *)pdata->iobase; + /* Hardcode for now */ + priv->emio = 0; + priv->phyaddr = -1; + + priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, + dev->of_offset, "phy-handle"); + if (priv->phy_of_handle > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, + priv->phy_of_handle, "reg", -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + priv->interface = pdata->phy_interface; + + priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio"); - return 1; + printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, + priv->phyaddr, phy_string_for_interface(priv->interface)); + + return 0; } + +static const struct udevice_id zynq_gem_ids[] = { + { .compatible = "cdns,zynqmp-gem" }, + { .compatible = "cdns,zynq-gem" }, + { .compatible = "cdns,gem" }, + { } +}; + +U_BOOT_DRIVER(zynq_gem) = { + .name = "zynq_gem", + .id = UCLASS_ETH, + .of_match = zynq_gem_ids, + .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, + .probe = zynq_gem_probe, + .remove = zynq_gem_remove, + .ops = &zynq_gem_ops, + .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +};