X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fphy%2Fvitesse.c;h=c58fe50b7206e8d6fd5e78e9dfaf8f510306d85f;hb=cc49da249cf2f380d2fed5571fad65ce6494fc95;hp=0a0f40dbde042558a8a9d1a5b4da48b96a3bb7ba;hpb=1c27059a2f7158a9c9a8778535b030935d75179d;p=oweals%2Fu-boot.git

diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 0a0f40dbde..c58fe50b72 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -4,20 +4,7 @@
  * Copyright 2010-2012 Freescale Semiconductor, Inc.
  * Author: Andy Fleming
  * Add vsc8662 phy support - Priyanka Jain
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <miiphy.h>
 
@@ -48,6 +35,36 @@
 #define MIIM_VSC8601_SKEW_CTRL		0x1c
 
 #define PHY_EXT_PAGE_ACCESS    0x1f
+#define PHY_EXT_PAGE_ACCESS_GENERAL	0x10
+#define PHY_EXT_PAGE_ACCESS_EXTENDED3	0x3
+
+/* Vitesse VSC8574 control register */
+#define MIIM_VSC8574_MAC_SERDES_CON	0x10
+#define MIIM_VSC8574_MAC_SERDES_ANEG	0x80
+#define MIIM_VSC8574_GENERAL18		0x12
+#define MIIM_VSC8574_GENERAL19		0x13
+
+/* Vitesse VSC8574 gerenal purpose register 18 */
+#define MIIM_VSC8574_18G_SGMII		0x80f0
+#define MIIM_VSC8574_18G_QSGMII		0x80e0
+#define MIIM_VSC8574_18G_CMDSTAT	0x8000
+
+/* Vitesse VSC8514 control register */
+#define MIIM_VSC8514_GENERAL18		0x12
+#define MIIM_VSC8514_GENERAL19		0x13
+#define MIIM_VSC8514_GENERAL23		0x17
+
+/* Vitesse VSC8514 gerenal purpose register 18 */
+#define MIIM_VSC8514_18G_QSGMII		0x80e0
+#define MIIM_VSC8514_18G_CMDSTAT	0x8000
+
+/* Vitesse VSC8664 Control/Status Register */
+#define MIIM_VSC8664_SERDES_AND_SIGDET	0x13
+#define MIIM_VSC8664_ADDITIONAL_DEV	0x16
+#define MIIM_VSC8664_EPHY_CON		0x17
+#define MIIM_VSC8664_LED_CON		0x1E
+
+#define PHY_EXT_PAGE_ACCESS_EXTENDED	0x0001
 
 /* CIS8201 */
 static int vitesse_config(struct phy_device *phydev)
@@ -123,7 +140,7 @@ static int cis8204_config(struct phy_device *phydev)
 }
 
 /* Vitesse VSC8601 */
-int vsc8601_config(struct phy_device *phydev)
+static int vsc8601_config(struct phy_device *phydev)
 {
 	/* Configure some basic stuff */
 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
@@ -145,6 +162,123 @@ int vsc8601_config(struct phy_device *phydev)
 	return 0;
 }
 
+static int vsc8574_config(struct phy_device *phydev)
+{
+	u32 val;
+	/* configure register 19G for MAC */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_GENERAL);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19);
+	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
+		/* set bit 15:14 to '01' for QSGMII mode */
+		val = (val & 0x3fff) | (1 << 14);
+		phy_write(phydev, MDIO_DEVAD_NONE,
+			  MIIM_VSC8574_GENERAL19, val);
+		/* Enable 4 ports MAC QSGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+			  MIIM_VSC8574_18G_QSGMII);
+	} else {
+		/* set bit 15:14 to '00' for SGMII mode */
+		val = val & 0x3fff;
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val);
+		/* Enable 4 ports MAC SGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+			  MIIM_VSC8574_18G_SGMII);
+	}
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
+	/* When bit 15 is cleared the command has completed */
+	while (val & MIIM_VSC8574_18G_CMDSTAT)
+		val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
+
+	/* Enable Serdes Auto-negotiation */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_EXTENDED3);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON);
+	val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
+static int vsc8514_config(struct phy_device *phydev)
+{
+	u32 val;
+	int timeout = 1000000;
+
+	/* configure register to access 19G */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_GENERAL);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19);
+	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
+		/* set bit 15:14 to '01' for QSGMII mode */
+		val = (val & 0x3fff) | (1 << 14);
+		phy_write(phydev, MDIO_DEVAD_NONE,
+			  MIIM_VSC8514_GENERAL19, val);
+		/* Enable 4 ports MAC QSGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18,
+			  MIIM_VSC8514_18G_QSGMII);
+	} else {
+		/*TODO Add SGMII functionality once spec sheet
+		 * for VSC8514 defines complete functionality
+		 */
+	}
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
+	/* When bit 15 is cleared the command has completed */
+	while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--)
+		val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
+
+	if (0 == timeout) {
+		printf("PHY 8514 config failed\n");
+		return -1;
+	}
+
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+	/* configure register to access 23 */
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23);
+	/* set bits 10:8 to '000' */
+	val = (val & 0xf8ff);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
+static int vsc8664_config(struct phy_device *phydev)
+{
+	u32 val;
+
+	/* Enable MAC interface auto-negotiation */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
+	val |= (1 << 13);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_EXTENDED);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
+	val |= (1 << 11);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+	/* Enable LED blink */
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
+	val &= ~(1 << 2);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
 static struct phy_driver VSC8211_driver = {
 	.name	= "Vitesse VSC8211",
 	.uid	= 0xfc4b0,
@@ -185,6 +319,26 @@ static struct phy_driver VSC8234_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver VSC8574_driver = {
+	.name = "Vitesse VSC8574",
+	.uid = 0x704a0,
+	.mask = 0xffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &vsc8574_config,
+	.startup = &vitesse_startup,
+	.shutdown = &genphy_shutdown,
+};
+
+static struct phy_driver VSC8514_driver = {
+	.name = "Vitesse VSC8514",
+	.uid = 0x70670,
+	.mask = 0xffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &vsc8514_config,
+	.startup = &vitesse_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 static struct phy_driver VSC8601_driver = {
 	.name = "Vitesse VSC8601",
 	.uid = 0x70420,
@@ -215,6 +369,16 @@ static struct phy_driver VSC8662_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver VSC8664_driver = {
+	.name = "Vitesse VSC8664",
+	.uid = 0x70660,
+	.mask = 0xffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &vsc8664_config,
+	.startup = &vitesse_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 /* Vitesse bought Cicada, so we'll put these here */
 static struct phy_driver cis8201_driver = {
 	.name = "CIS8201",
@@ -244,7 +408,10 @@ int phy_vitesse_init(void)
 	phy_register(&VSC8244_driver);
 	phy_register(&VSC8211_driver);
 	phy_register(&VSC8221_driver);
+	phy_register(&VSC8574_driver);
+	phy_register(&VSC8514_driver);
 	phy_register(&VSC8662_driver);
+	phy_register(&VSC8664_driver);
 	phy_register(&cis8201_driver);
 	phy_register(&cis8204_driver);