X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fftmac110.h;h=2772ae7b703e0e583fa3da81cd4c4b6ce6bc5e50;hb=8a33cb8b6bdf8a35f931fcc3d8aa15254cfc4b23;hp=19e4248bd3859fc6204cf336207b7f0ec82e59ee;hpb=8b485ba12b0defa0c4ed3559789250238f8331a8;p=oweals%2Fu-boot.git diff --git a/drivers/net/ftmac110.h b/drivers/net/ftmac110.h index 19e4248bd3..2772ae7b70 100644 --- a/drivers/net/ftmac110.h +++ b/drivers/net/ftmac110.h @@ -1,7 +1,7 @@ /* * Faraday 10/100Mbps Ethernet Controller * - * (C) Copyright 2010 Faraday Technology + * (C) Copyright 2013 Faraday Technology * Dante Su * * SPDX-License-Identifier: GPL-2.0+ @@ -135,42 +135,42 @@ struct ftmac110_regs { /* * descriptor structure */ -struct ftmac110_rxd { - uint32_t ct[2]; - uint32_t buf; - void *vbuf; /* reserved */ +struct ftmac110_desc { + uint64_t ctrl; + uint32_t pbuf; + void *vbuf; }; -#define FTMAC110_RXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */ -#define FTMAC110_RXCT0_FRS BIT_MASK(29) /* first pkt desc */ -#define FTMAC110_RXCT0_LRS BIT_MASK(28) /* last pkt desc */ -#define FTMAC110_RXCT0_ODDNB BIT_MASK(22) /* odd nibble */ -#define FTMAC110_RXCT0_RUNT BIT_MASK(21) /* runt pkt */ -#define FTMAC110_RXCT0_FTL BIT_MASK(20) /* frame too long */ -#define FTMAC110_RXCT0_CRC BIT_MASK(19) /* pkt crc error */ -#define FTMAC110_RXCT0_ERR BIT_MASK(18) /* bus error */ -#define FTMAC110_RXCT0_ERRMASK (0x1f << 18) /* all errors */ -#define FTMAC110_RXCT0_BCST BIT_MASK(17) /* Bcst pkt */ -#define FTMAC110_RXCT0_MCST BIT_MASK(16) /* Mcst pkt */ -#define FTMAC110_RXCT0_LEN(x) ((x) & 0x7ff) - -#define FTMAC110_RXCT1_END BIT_MASK(31) -#define FTMAC110_RXCT1_BUFSZ(x) ((x) & 0x7ff) - -struct ftmac110_txd { - uint32_t ct[2]; - uint32_t buf; - void *vbuf; /* reserved */ -}; - -#define FTMAC110_TXCT0_OWNER BIT_MASK(31) /* owner: 1=HW, 0=SW */ -#define FTMAC110_TXCT0_COL 0x00000003 /* collision */ - -#define FTMAC110_TXCT1_END BIT_MASK(31) /* end of ring */ -#define FTMAC110_TXCT1_TXIC BIT_MASK(30) /* tx done interrupt */ -#define FTMAC110_TXCT1_TX2FIC BIT_MASK(29) /* tx fifo interrupt */ -#define FTMAC110_TXCT1_FTS BIT_MASK(28) /* first pkt desc */ -#define FTMAC110_TXCT1_LTS BIT_MASK(27) /* last pkt desc */ -#define FTMAC110_TXCT1_LEN(x) ((x) & 0x7ff) +#define FTMAC110_RXD_END ((uint64_t)1 << 63) +#define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32) + +#define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ +#define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */ +#define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */ +#define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */ +#define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */ +#define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */ +#define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */ +#define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */ +#define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18) +#define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */ +#define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */ +#define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff)) + +#define FTMAC110_RXD_CLRMASK \ + (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff)) + +#define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */ +#define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */ +#define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */ +#define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */ +#define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */ +#define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32) + +#define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */ +#define FTMAC110_TXD_COL ((uint64_t)3) /* collision */ + +#define FTMAC110_TXD_CLRMASK \ + (FTMAC110_TXD_END) #endif /* FTMAC110_H */