X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fnet%2Fdesignware.c;h=d9cb5076951a9a5c5576c434a734e45bf7976c46;hb=59370f3fcd135089c402c93720a87c688abe600c;hp=933032cfdef56b08300b4c88141e4e1a7a745d45;hpb=aa51005c3f7e517164fa000d68672041f6c4191f;p=oweals%2Fu-boot.git diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 933032cfde..d9cb507695 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -2,39 +2,97 @@ * (C) Copyright 2010 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* - * Designware ethernet IP driver for u-boot + * Designware ethernet IP driver for U-Boot */ #include +#include +#include #include #include +#include #include #include #include "designware.h" -static void tx_descs_init(struct eth_device *dev) +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_PHYLIB) +# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -ETIMEDOUT; +} + +static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = dw_mdio_read; + bus->write = dw_mdio_write; + snprintf(bus->name, sizeof(bus->name), name); + + bus->priv = (void *)mac_regs_p; + + return mdio_register(bus); +} + +static void tx_descs_init(struct dw_eth_dev *priv) { - struct dw_eth_dev *priv = dev->priv; struct eth_dma_regs *dma_p = priv->dma_regs_p; struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; char *txbuffs = &priv->txbuffs[0]; @@ -64,18 +122,32 @@ static void tx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->tx_mac_descrtable, + (unsigned int)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + priv->tx_currdescnum = 0; } -static void rx_descs_init(struct eth_device *dev) +static void rx_descs_init(struct dw_eth_dev *priv) { - struct dw_eth_dev *priv = dev->priv; struct eth_dma_regs *dma_p = priv->dma_regs_p; struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; char *rxbuffs = &priv->rxbuffs[0]; struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; @@ -91,110 +163,160 @@ static void rx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->rx_mac_descrtable, + (unsigned int)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + priv->rx_currdescnum = 0; } -static void descs_init(struct eth_device *dev) +static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) { - tx_descs_init(dev); - rx_descs_init(dev); + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; } -static int mac_reset(struct eth_device *dev) +static void dw_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } - int timeout = CONFIG_MACRESET_TIMEOUT; + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; - writel(DMAMAC_SRST, &dma_p->busmode); - writel(MII_PORTSELECT, &mac_p->conf); + if (phydev->speed == 100) + conf |= FES_100; - do { - if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) - return 0; - udelay(1000); - } while (timeout--); + if (phydev->duplex) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); - return -1; + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } -static int dw_write_hwaddr(struct eth_device *dev) +static void _dw_eth_halt(struct dw_eth_dev *priv) { - struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 macid_lo, macid_hi; - u8 *mac_id = &dev->enetaddr[0]; - - macid_lo = mac_id[0] + (mac_id[1] << 8) + \ - (mac_id[2] << 16) + (mac_id[3] << 24); - macid_hi = mac_id[4] + (mac_id[5] << 8); + struct eth_dma_regs *dma_p = priv->dma_regs_p; - writel(macid_hi, &mac_p->macaddr0hi); - writel(macid_lo, &mac_p->macaddr0lo); + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); - return 0; + phy_shutdown(priv->phydev); } -static int dw_eth_init(struct eth_device *dev, bd_t *bis) +static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) { - struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - u32 conf; + unsigned int start; + int ret; - /* Reset ethernet hardware */ - if (mac_reset(dev) < 0) - return -1; + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); - /* Resore the HW MAC address as it has been lost during MAC reset */ - dw_write_hwaddr(dev); + start = get_timer(0); + while (readl(&dma_p->busmode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { + printf("DMA reset timeout\n"); + return -ETIMEDOUT; + } - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, - &dma_p->busmode); + mdelay(100); + }; - writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); - writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + /* + * Soft reset above clears HW address registers. + * So we have to set it here once again. + */ + _dw_write_hwaddr(priv, enetaddr); - conf = FRAMEBURSTENABLE | DISABLERXOWN; + rx_descs_init(priv); + tx_descs_init(priv); - if (priv->speed != SPEED_1000M) - conf |= MII_PORTSELECT; + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); - if (priv->duplex == FULL_DUPLEX) - conf |= FULLDPLXMODE; +#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, + &dma_p->opmode); +#else + writel(readl(&dma_p->opmode) | FLUSHTXFIFO, + &dma_p->opmode); +#endif - writel(conf, &mac_p->conf); + writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); - descs_init(dev); +#ifdef CONFIG_DW_AXI_BURST_LEN + writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); +#endif - /* - * Start/Enable xfer at dma as well as mac level - */ - writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); - writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + /* Start up the PHY */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } + + dw_adjust_link(mac_p, priv->phydev); + + if (!priv->phydev->link) + return -EIO; writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); return 0; } -static int dw_eth_send(struct eth_device *dev, volatile void *packet, - int length) +static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) { - struct dw_eth_dev *priv = dev->priv; struct eth_dma_regs *dma_p = priv->dma_regs_p; u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end = data_start + + roundup(length, ARCH_DMA_MINALIGN); + /* + * Strictly we only need to invalidate the "txrx_status" field + * for the following check, but on some platforms we cannot + * invalidate only 4 bytes, so we flush the entire descriptor, + * which is 16 bytes in total. This is safe because the + * individual descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN and padded appropriately. + */ + invalidate_dcache_range(desc_start, desc_end); /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { printf("CPU not owner of tx frame\n"); - return -1; + return -EPERM; } - memcpy((void *)desc_p->dmamac_addr, (void *)packet, length); + memcpy(desc_p->dmamac_addr, packet, length); + + /* Flush data to be sent */ + flush_dcache_range(data_start, data_end); #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; @@ -211,6 +333,9 @@ static int dw_eth_send(struct eth_device *dev, volatile void *packet, desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; #endif + /* Flush modified buffer descriptor */ + flush_dcache_range(desc_start, desc_end); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) desc_num = 0; @@ -223,14 +348,21 @@ static int dw_eth_send(struct eth_device *dev, volatile void *packet, return 0; } -static int dw_eth_recv(struct eth_device *dev) +static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) { - struct dw_eth_dev *priv = dev->priv; - u32 desc_num = priv->rx_currdescnum; + u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + int length = -EAGAIN; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + uint32_t data_start = (uint32_t)desc_p->dmamac_addr; + uint32_t data_end; - u32 status = desc_p->txrx_status; - int length = 0; + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + status = desc_p->txrx_status; /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { @@ -238,251 +370,101 @@ static int dw_eth_recv(struct eth_device *dev) length = (status & DESC_RXSTS_FRMLENMSK) >> \ DESC_RXSTS_FRMLENSHFT; - NetReceive(desc_p->dmamac_addr, length); - - /* - * Make the current descriptor valid again and go to - * the next one - */ - desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; - - /* Test the wrap-around condition. */ - if (++desc_num >= CONFIG_RX_DESCR_NUM) - desc_num = 0; + /* Invalidate received data */ + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); + *packetp = desc_p->dmamac_addr; } - priv->rx_currdescnum = desc_num; - return length; } -static void dw_eth_halt(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - - mac_reset(dev); - priv->tx_currdescnum = priv->rx_currdescnum = 0; -} - -static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +static int _dw_free_pkt(struct dw_eth_dev *priv) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 miiaddr; - int timeout = CONFIG_MDIO_TIMEOUT; + u32 desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK); + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + /* Flush only status field - others weren't changed */ + flush_dcache_range(desc_start, desc_end); - do { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - *val = readl(&mac_p->miidata); - return 0; - } - udelay(1000); - } while (timeout--); + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + priv->rx_currdescnum = desc_num; - return -1; + return 0; } -static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) +static int dw_phy_init(struct dw_eth_dev *priv, void *dev) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 miiaddr; - int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; - u16 value; + struct phy_device *phydev; + int mask = 0xffffffff; - writel(val, &mac_p->miidata); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; +#endif - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) + return -ENODEV; - do { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - ret = 0; - break; - } - udelay(1000); - } while (timeout--); + phy_connect_dev(phydev, dev); - /* Needed as a fix for ST-Phy */ - eth_mdio_read(dev, addr, reg, &value); + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; - return ret; + priv->phydev = phydev; + phy_config(phydev); + + return 0; } -#if defined(CONFIG_DW_SEARCH_PHY) -static int find_phy(struct eth_device *dev) +#ifndef CONFIG_DM_ETH +static int dw_eth_init(struct eth_device *dev, bd_t *bis) { - int phy_addr = 0; - u16 ctrl, oldctrl; - - do { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - oldctrl = ctrl & BMCR_ANENABLE; - - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - ctrl &= BMCR_ANENABLE; - - if (ctrl == oldctrl) { - phy_addr++; - } else { - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - - return phy_addr; - } - } while (phy_addr < 32); - - return -1; + return _dw_eth_init(dev->priv, dev->enetaddr); } -#endif -static int dw_reset_phy(struct eth_device *dev) +static int dw_eth_send(struct eth_device *dev, void *packet, int length) { - struct dw_eth_dev *priv = dev->priv; - u16 ctrl; - int timeout = CONFIG_PHYRESET_TIMEOUT; - u32 phy_addr = priv->address; - - eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); - do { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - if (!(ctrl & BMCR_RESET)) - break; - udelay(1000); - } while (timeout--); - - if (timeout < 0) - return -1; - -#ifdef CONFIG_PHY_RESET_DELAY - udelay(CONFIG_PHY_RESET_DELAY); -#endif - return 0; + return _dw_eth_send(dev->priv, packet, length); } -static int configure_phy(struct eth_device *dev) +static int dw_eth_recv(struct eth_device *dev) { - struct dw_eth_dev *priv = dev->priv; - int phy_addr; - u16 bmcr; -#if defined(CONFIG_DW_AUTONEG) - u16 bmsr; - u32 timeout; - u16 anlpar, btsr; -#else - u16 ctrl; -#endif + uchar *packet; + int length; -#if defined(CONFIG_DW_SEARCH_PHY) - phy_addr = find_phy(dev); - if (phy_addr >= 0) - priv->address = phy_addr; - else - return -1; -#else - phy_addr = priv->address; -#endif - if (dw_reset_phy(dev) < 0) - return -1; + length = _dw_eth_recv(dev->priv, &packet); + if (length == -EAGAIN) + return 0; + net_process_received_packet(packet, length); -#if defined(CONFIG_DW_AUTONEG) - bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \ - BMCR_FULLDPLX | BMCR_SPEED1000; -#else - bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; + _dw_free_pkt(dev->priv); -#if defined(CONFIG_DW_SPEED10M) - bmcr &= ~BMCR_SPEED100; -#endif -#if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~BMCR_FULLDPLX; -#endif -#endif - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - - /* Read the phy status register and populate priv structure */ -#if defined(CONFIG_DW_AUTONEG) - timeout = CONFIG_AUTONEG_TIMEOUT; - do { - eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) - break; - udelay(1000); - } while (timeout--); - - eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); - eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); - - if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { - priv->speed = SPEED_1000M; - if (btsr & PHY_1000BTSR_1000FD) - priv->duplex = FULL_DUPLEX; - else - priv->duplex = HALF_DUPLEX; - } else { - if (anlpar & LPA_100) - priv->speed = SPEED_100M; - else - priv->speed = SPEED_10M; - - if (anlpar & (LPA_10FULL | LPA_100FULL)) - priv->duplex = FULL_DUPLEX; - else - priv->duplex = HALF_DUPLEX; - } -#else - if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) - return -1; - - if (ctrl & BMCR_FULLDPLX) - priv->duplex = FULL_DUPLEX; - else - priv->duplex = HALF_DUPLEX; - - if (ctrl & BMCR_SPEED1000) - priv->speed = SPEED_1000M; - else if (ctrl & BMCR_SPEED100) - priv->speed = SPEED_100M; - else - priv->speed = SPEED_10M; -#endif return 0; } -#if defined(CONFIG_MII) -static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) +static void dw_eth_halt(struct eth_device *dev) { - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_read(dev, addr, reg, val); - - return 0; + return _dw_eth_halt(dev->priv); } -static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) +static int dw_write_hwaddr(struct eth_device *dev) { - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_write(dev, addr, reg, val); - - return 0; + return _dw_write_hwaddr(dev->priv, dev->enetaddr); } -#endif -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) +int designware_initialize(ulong base_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -495,7 +477,8 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) * Since the priv structure contains the descriptors which need a strict * buswidth alignment, memalign is used to allocate memory */ - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, + sizeof(struct dw_eth_dev)); if (!priv) { free(dev); return -ENOMEM; @@ -504,25 +487,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) memset(dev, 0, sizeof(struct eth_device)); memset(priv, 0, sizeof(struct dw_eth_dev)); - sprintf(dev->name, "mii%d", id); + sprintf(dev->name, "dwmac.%lx", base_addr); dev->iobase = (int)base_addr; dev->priv = priv; - eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); - priv->dev = dev; priv->mac_regs_p = (struct eth_mac_regs *)base_addr; priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + DW_DMA_BASE_OFFSET); - priv->address = phy_addr; - - if (mac_reset(dev) < 0) - return -1; - - if (configure_phy(dev) < 0) { - printf("Phy could not be configured\n"); - return -1; - } dev->init = dw_eth_init; dev->send = dw_eth_send; @@ -532,8 +504,123 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) eth_register(dev); -#if defined(CONFIG_MII) - miiphy_register(dev->name, dw_mii_read, dw_mii_write); + priv->interface = interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_phy_init(priv, dev); +} #endif - return 1; + +#ifdef CONFIG_DM_ETH +static int designware_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + return _dw_eth_init(dev->priv, pdata->enetaddr); +} + +static int designware_eth_send(struct udevice *dev, void *packet, int length) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_eth_send(priv, packet, length); +} + +static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_eth_recv(priv, packetp); +} + +static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_free_pkt(priv); } + +static void designware_eth_stop(struct udevice *dev) +{ + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_eth_halt(priv); +} + +static int designware_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + + return _dw_write_hwaddr(priv, pdata->enetaddr); +} + +static int designware_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + int ret; + + debug("%s, iobase=%lx, priv=%p\n", __func__, pdata->iobase, priv); + priv->mac_regs_p = (struct eth_mac_regs *)pdata->iobase; + priv->dma_regs_p = (struct eth_dma_regs *)(pdata->iobase + + DW_DMA_BASE_OFFSET); + priv->interface = pdata->phy_interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = dw_phy_init(priv, dev); + debug("%s, ret=%d\n", __func__, ret); + + return ret; +} + +static const struct eth_ops designware_eth_ops = { + .start = designware_eth_start, + .send = designware_eth_send, + .recv = designware_eth_recv, + .free_pkt = designware_eth_free_pkt, + .stop = designware_eth_stop, + .write_hwaddr = designware_eth_write_hwaddr, +}; + +static int designware_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + + pdata->iobase = dev_get_addr(dev); + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + return 0; +} + +static const struct udevice_id designware_eth_ids[] = { + { .compatible = "allwinner,sun7i-a20-gmac" }, + { .compatible = "altr,socfpga-stmmac" }, + { } +}; + +U_BOOT_DRIVER(eth_designware) = { + .name = "eth_designware", + .id = UCLASS_ETH, + .of_match = designware_eth_ids, + .ofdata_to_platdata = designware_eth_ofdata_to_platdata, + .probe = designware_eth_probe, + .ops = &designware_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif