X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fnet%2Faltera_tse.c;h=de517f8dab9493f2a8492a8aa8ecc59d3d50b1ab;hb=6defdc0b5552ab1af4a66a8abac8196cbb6b9e15;hp=d45aab13062375e292f9b70cf019985995fe5d8d;hpb=09b4a9cf4003599f2cd609587dfa5f0b754640ed;p=oweals%2Fu-boot.git diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index d45aab1306..de517f8dab 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -198,6 +198,12 @@ static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev, if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) debug("Timeout waiting sgdma in do async!\n"); + /* + * Clear the RUN bit in the control register. This is needed + * to restart the SGDMA engine later on. + */ + dev->control = 0; + /* * Clear any (previous) status register information * that might occlude our error checking later. @@ -251,8 +257,7 @@ static int tse_adjust_link(struct altera_tse_priv *priv) return 0; } -static int tse_eth_send(struct eth_device *dev, - volatile void *packet, int length) +static int tse_eth_send(struct eth_device *dev, void *packet, int length) { struct altera_tse_priv *priv = dev->priv; volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; @@ -262,7 +267,8 @@ static int tse_eth_send(struct eth_device *dev, volatile struct alt_sgdma_descriptor *tx_desc_cur = (volatile struct alt_sgdma_descriptor *)&tx_desc[0]; - flush_dcache((unsigned long)packet, length); + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + length); alt_sgdma_construct_descriptor_burst( (volatile struct alt_sgdma_descriptor *)&tx_desc[0], (volatile struct alt_sgdma_descriptor *)&tx_desc[1], @@ -300,7 +306,8 @@ static int tse_eth_rx(struct eth_device *dev) NetReceive(NetRxPackets[0], packet_length); /* start descriptor again */ - flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + flush_dcache_range((unsigned long)(NetRxPackets[0]), + (unsigned long)(NetRxPackets[0]) + PKTSIZE_ALIGN); alt_sgdma_construct_descriptor_burst( (volatile struct alt_sgdma_descriptor *)&rx_desc[0], (volatile struct alt_sgdma_descriptor *)&rx_desc[1], @@ -317,6 +324,8 @@ static int tse_eth_rx(struct eth_device *dev) /* setup the sgdma */ alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]); + + return packet_length; } return -1; @@ -351,8 +360,8 @@ static void tse_eth_reset(struct eth_device *dev) if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { debug("Timeout waiting for rx sgdma!\n"); - rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; - rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; } counter = 0; @@ -364,8 +373,8 @@ static void tse_eth_reset(struct eth_device *dev) if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { debug("Timeout waiting for tx sgdma!\n"); - tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; - tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; } /* reset the mac */ mac_dev->command_config.bits.transmit_enable = 1; @@ -475,12 +484,12 @@ static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) */ mii_reg = tse_mdio_read(priv, MIIM_STATUS); - if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) - && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE) + && !(mii_reg & BMSR_ANEGCOMPLETE)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); - while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + while (!(mii_reg & BMSR_ANEGCOMPLETE)) { /* * Timeout reached ? */ @@ -577,7 +586,11 @@ static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv) { uint mii_data = tse_mdio_read(priv, mii_reg); mii_data &= 0xfff0; - mii_data |= 0xb; + if ((priv->flags >= 1) && (priv->flags <= 4)) + mii_data |= 0xb; + else if (priv->flags == 5) + mii_data |= 0x4; + return mii_data; } @@ -585,7 +598,9 @@ static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv) { uint mii_data = tse_mdio_read(priv, mii_reg); mii_data &= ~0x82; - mii_data |= 0x82; + if ((priv->flags >= 1) && (priv->flags <= 4)) + mii_data |= 0x82; + return mii_data; } @@ -643,13 +658,13 @@ static struct phy_info phy_info_generic = { "Unknown/Generic PHY", 32, (struct phy_cmd[]){ /* config */ - {PHY_BMCR, PHY_BMCR_RESET, NULL}, - {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL}, + {MII_BMCR, BMCR_RESET, NULL}, + {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL}, {miim_end,} }, (struct phy_cmd[]){ /* startup */ - {PHY_BMSR, miim_read, NULL}, - {PHY_BMSR, miim_read, &mii_parse_sr}, + {MII_BMSR, miim_read, NULL}, + {MII_BMSR, miim_read, &mii_parse_sr}, {miim_end,} }, (struct phy_cmd[]){ /* shutdown */ @@ -820,7 +835,8 @@ static int tse_eth_init(struct eth_device *dev, bd_t * bd) 0x0 /* channel */ ); debug("Configuring rx desc\n"); - flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + flush_dcache_range((unsigned long)(NetRxPackets[0]), + (unsigned long)(NetRxPackets[0]) + PKTSIZE_ALIGN); alt_sgdma_construct_descriptor_burst( (volatile struct alt_sgdma_descriptor *)&rx_desc[0], (volatile struct alt_sgdma_descriptor *)&rx_desc[1], @@ -876,7 +892,8 @@ static int tse_eth_init(struct eth_device *dev, bd_t * bd) /* TSE init code */ int altera_tse_initialize(u8 dev_num, int mac_base, - int sgdma_rx_base, int sgdma_tx_base) + int sgdma_rx_base, int sgdma_tx_base, + u32 sgdma_desc_base, u32 sgdma_desc_size) { struct altera_tse_priv *priv; struct eth_device *dev; @@ -897,8 +914,20 @@ int altera_tse_initialize(u8 dev_num, int mac_base, free(dev); return 0; } - tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), - &dma_handle); + if (sgdma_desc_size) { + if (sgdma_desc_size < (sizeof(*tx_desc) * (3 + PKTBUFSRX))) { + printf("ALTERA_TSE-%hu: " + "descriptor memory is too small\n", dev_num); + free(priv); + free(dev); + return 0; + } + tx_desc = (struct alt_sgdma_descriptor *)sgdma_desc_base; + } else { + tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), + &dma_handle); + } + rx_desc = tx_desc + 2; debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc); debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc);