X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fmmc%2Fstm32_sdmmc2.c;h=b802316720a5b7ce140d387e9bc4c036e26f1072;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=3e578359e02aadeef4cff05f7a5742eaf91843b1;hpb=a72dd8ed95992be67a03073dd28dad27618e5a39;p=oweals%2Fu-boot.git diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 3e578359e0..b802316720 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -1,20 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved * Author(s): Patrice Chotard, for STMicroelectronics. - * - * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include #include #include +#include +#include +#include +#include #include #include #include #include #include #include +#include struct stm32_sdmmc2_plat { struct mmc_config cfg; @@ -57,7 +62,10 @@ struct stm32_sdmmc2_ctx { #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */ /* SDMMC_POWER register */ -#define SDMMC_POWER_PWRCTRL GENMASK(1, 0) +#define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0) +#define SDMMC_POWER_PWRCTRL_OFF 0 +#define SDMMC_POWER_PWRCTRL_CYCLE 2 +#define SDMMC_POWER_PWRCTRL_ON 3 #define SDMMC_POWER_VSWITCH BIT(2) #define SDMMC_POWER_VSWITCHEN BIT(3) #define SDMMC_POWER_DIRPOL BIT(4) @@ -72,7 +80,10 @@ struct stm32_sdmmc2_ctx { #define SDMMC_CLKCR_HWFC_EN BIT(17) #define SDMMC_CLKCR_DDR BIT(18) #define SDMMC_CLKCR_BUSSPEED BIT(19) -#define SDMMC_CLKCR_SELCLKRX GENMASK(21, 20) +#define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20) +#define SDMMC_CLKCR_SELCLKRX_CK 0 +#define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20) +#define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21) /* SDMMC_CMD register */ #define SDMMC_CMD_CMDINDEX GENMASK(5, 0) @@ -185,8 +196,7 @@ struct stm32_sdmmc2_ctx { #define SDMMC_IDMACTRL_IDMAEN BIT(0) #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF - -DECLARE_GLOBAL_DATA_PTR; +#define SDMMC_BUSYD0END_TIMEOUT_US 2000000 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, struct mmc_data *data, @@ -206,9 +216,6 @@ static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, idmabase0 = (u32)data->src; } - /* Set the SDMMC Data TimeOut value */ - writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER); - /* Set the SDMMC DataLength value */ writel(ctx->data_length, priv->base + SDMMC_DLEN); @@ -233,10 +240,13 @@ static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, } static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv, - struct mmc_cmd *cmd, u32 cmd_param) + struct mmc_cmd *cmd, u32 cmd_param, + struct stm32_sdmmc2_ctx *ctx) { - if (readl(priv->base + SDMMC_ARG) & SDMMC_CMD_CPSMEN) - writel(0, priv->base + SDMMC_ARG); + u32 timeout = 0; + + if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN) + writel(0, priv->base + SDMMC_CMD); cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN; if (cmd->resp_type & MMC_RSP_PRESENT) { @@ -248,6 +258,26 @@ static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv, cmd_param |= SDMMC_CMD_WAITRESP_1; } + /* + * SDMMC_DTIME must be set in two case: + * - on data transfert. + * - on busy request. + * If not done or too short, the dtimeout flag occurs and DPSM stays + * enabled/busy and waits for abort (stop transmission cmd). + * Next data command is not possible whereas DPSM is activated. + */ + if (ctx->data_length) { + timeout = SDMMC_CMD_TIMEOUT; + } else { + writel(0, priv->base + SDMMC_DCTRL); + + if (cmd->resp_type & MMC_RSP_BUSY) + timeout = SDMMC_CMD_TIMEOUT; + } + + /* Set the SDMMC Data TimeOut value */ + writel(timeout, priv->base + SDMMC_DTIMER); + /* Clear flags */ writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); @@ -306,6 +336,31 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv, cmd->response[2] = readl(priv->base + SDMMC_RESP3); cmd->response[3] = readl(priv->base + SDMMC_RESP4); } + + /* Wait for BUSYD0END flag if busy status is detected */ + if (cmd->resp_type & MMC_RSP_BUSY && + status & SDMMC_STA_BUSYD0) { + mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END; + + /* Polling status register */ + ret = readl_poll_timeout(priv->base + SDMMC_STA, + status, status & mask, + SDMMC_BUSYD0END_TIMEOUT_US); + + if (ret < 0) { + debug("%s: timeout reading SDMMC_STA\n", + __func__); + ctx->dpsm_abort = true; + return ret; + } + + if (status & SDMMC_STA_DTIMEOUT) { + debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n", + __func__, status); + ctx->dpsm_abort = true; + return -ETIMEDOUT; + } + } } return 0; @@ -383,6 +438,8 @@ static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0; int ret, retry = 3; + WATCHDOG_RESET(); + retry_cmd: ctx.data_length = 0; ctx.dpsm_abort = false; @@ -392,7 +449,7 @@ retry_cmd: stm32_sdmmc2_start_data(priv, data, &ctx); } - stm32_sdmmc2_start_cmd(priv, cmd, cmdat); + stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx); debug("%s: send cmd %d data: 0x%x @ 0x%x\n", __func__, cmd->cmdidx, @@ -422,7 +479,10 @@ retry_cmd: debug("%s: send STOP command to abort dpsm treatments\n", __func__); - stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP); + ctx.data_length = 0; + + stm32_sdmmc2_start_cmd(priv, &stop_cmd, + SDMMC_CMD_CMDSTOP, &ctx); stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx); writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); @@ -440,23 +500,72 @@ retry_cmd: return ret; } -static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) +/* + * Reset the SDMMC with the RCC.SDMMCxRST register bit. + * This will reset the SDMMC to the reset state and the CPSM and DPSM + * to the Idle state. SDMMC is disabled, Signals Hiz. + */ +static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv) { /* Reset */ reset_assert(&priv->reset_ctl); udelay(2); reset_deassert(&priv->reset_ctl); - udelay(1000); + /* init the needed SDMMC register after reset */ + writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER); +} + +/* + * Set the SDMMC in power-cycle state. + * This will make that the SDMMC_D[7:0], + * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being + * supplied through the signal lines. + */ +static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv) +{ + if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) == + SDMMC_POWER_PWRCTRL_CYCLE) + return; + + stm32_sdmmc2_reset(priv); +} + +/* + * set the SDMMC state Power-on: the card is clocked + * manage the SDMMC state control: + * Reset => Power-Cycle => Power-Off => Power + * PWRCTRL=10 PWCTRL=00 PWCTRL=11 + */ +static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) +{ + u32 pwrctrl = + readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK; + + if (pwrctrl == SDMMC_POWER_PWRCTRL_ON) + return; - /* Set Power State to ON */ - writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER); + /* warning: same PWRCTRL value after reset and for power-off state + * it is the reset state here = the only managed by the driver + */ + if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) { + writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); + } /* - * 1ms: required power up waiting time before starting the - * SD initialization sequence + * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE + * switch to Power-Off state: SDMCC disable, signals drive 1 */ - udelay(1000); + writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); + + /* After the 1ms delay set the SDMMC to power-on */ + mdelay(1); + writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); + + /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */ } #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1) @@ -464,8 +573,6 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); - struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev); - struct mmc_config *cfg = &plat->cfg; u32 desired = mmc->clock; u32 sys_clock = clk_get_rate(&priv->clk); u32 clk = 0; @@ -473,7 +580,9 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) debug("%s: bus_with = %d, clock = %d\n", __func__, mmc->bus_width, mmc->clock); - if ((mmc->bus_width == 1) && (desired == cfg->f_min)) + if (mmc->clk_disable) + stm32_sdmmc2_pwrcycle(priv); + else stm32_sdmmc2_pwron(priv); /* @@ -513,10 +622,21 @@ static int stm32_sdmmc2_getcd(struct udevice *dev) return 1; } +static int stm32_sdmmc2_host_power_cycle(struct udevice *dev) +{ + struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + + writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, + priv->base + SDMMC_POWER); + + return 0; +} + static const struct dm_mmc_ops stm32_sdmmc2_ops = { .send_cmd = stm32_sdmmc2_send_cmd, .set_ios = stm32_sdmmc2_set_ios, .get_cd = stm32_sdmmc2_getcd, + .host_power_cycle = stm32_sdmmc2_host_power_cycle, }; static int stm32_sdmmc2_probe(struct udevice *dev) @@ -531,10 +651,12 @@ static int stm32_sdmmc2_probe(struct udevice *dev) if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; - if (dev_read_bool(dev, "st,negedge")) + if (dev_read_bool(dev, "st,neg-edge")) priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; - if (dev_read_bool(dev, "st,dirpol")) + if (dev_read_bool(dev, "st,sig-dir")) priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL; + if (dev_read_bool(dev, "st,use-ckin")) + priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; ret = clk_get_by_index(dev, 0, &priv->clk); if (ret) @@ -555,7 +677,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev) cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - cfg->name = "STM32 SDMMC2"; + cfg->name = "STM32 SD/MMC"; cfg->host_caps = 0; if (cfg->f_max > 25000000) @@ -564,6 +686,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev) switch (dev_read_u32_default(dev, "bus-width", 1)) { case 8: cfg->host_caps |= MMC_MODE_8BIT; + /* fall through */ case 4: cfg->host_caps |= MMC_MODE_4BIT; break; @@ -575,6 +698,8 @@ static int stm32_sdmmc2_probe(struct udevice *dev) upriv->mmc = &plat->mmc; + /* SDMMC init */ + stm32_sdmmc2_reset(priv); return 0; clk_disable: @@ -585,7 +710,7 @@ clk_free: return ret; } -int stm32_sdmmc_bind(struct udevice *dev) +static int stm32_sdmmc_bind(struct udevice *dev) { struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);