X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fmmc%2Fmv_sdhci.c;h=69aa87babe13089057454d8e9c655cc8eb2d93db;hb=20b9f2eaf5fbb1e7befbdc4f7863fd69c942d744;hp=2fe34b6993b8a8a006da4d0ae5704e1d1e0f66a7;hpb=6d7ba2cef52d6daf119269f06c471c8882e59b84;p=oweals%2Fu-boot.git

diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 2fe34b6993..69aa87babe 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -1,6 +1,41 @@
+/*
+ * Marvell SD Host Controller Interface
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
 #include <common.h>
 #include <malloc.h>
 #include <sdhci.h>
+#include <linux/mbus.h>
+
+#define SDHCI_WINDOW_CTRL(win)		(0x4080 + ((win) << 4))
+#define SDHCI_WINDOW_BASE(win)		(0x4084 + ((win) << 4))
+
+static void sdhci_mvebu_mbus_config(void __iomem *base)
+{
+	const struct mbus_dram_target_info *dram;
+	int i;
+
+	dram = mvebu_mbus_dram_info();
+
+	for (i = 0; i < 4; i++) {
+		writel(0, base + SDHCI_WINDOW_CTRL(i));
+		writel(0, base + SDHCI_WINDOW_BASE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		const struct mbus_dram_window *cs = dram->cs + i;
+
+		/* Write size, attributes and target id to control register */
+		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+		       (dram->mbus_dram_target_id << 4) | 1,
+		       base + SDHCI_WINDOW_CTRL(i));
+
+		/* Write base address to base register */
+		writel(cs->base, base + SDHCI_WINDOW_BASE(i));
+	}
+}
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 static struct sdhci_ops mv_ops;
@@ -12,7 +47,7 @@ static struct sdhci_ops mv_ops;
 static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
 	struct mmc *mmc = host->mmc;
-	u32 ata = (u32)host->ioaddr + SD_CE_ATA_2;
+	u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
 
 	if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
 		if (mmc->bus_width == 8)
@@ -30,27 +65,29 @@ static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 
 static char *MVSDH_NAME = "mv_sdh";
-int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
+int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
 {
 	struct sdhci_host *host = NULL;
 	host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
 	if (!host) {
 		printf("sdh_host malloc fail!\n");
-		return 1;
+		return -ENOMEM;
 	}
 
 	host->name = MVSDH_NAME;
 	host->ioaddr = (void *)regbase;
 	host->quirks = quirks;
+	host->max_clk = max_clk;
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 	memset(&mv_ops, 0, sizeof(struct sdhci_ops));
 	mv_ops.write_b = mv_sdhci_writeb;
 	host->ops = &mv_ops;
 #endif
-	if (quirks & SDHCI_QUIRK_REG32_RW)
-		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
-	else
-		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
-	add_sdhci(host, max_clk, min_clk);
-	return 0;
+
+	if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
+		/* Configure SDHCI MBUS mbus bridge windows */
+		sdhci_mvebu_mbus_config((void __iomem *)regbase);
+	}
+
+	return add_sdhci(host, 0, min_clk);
 }