X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Ffpga%2Fvirtex2.c;h=0d2d9a4693264684bbeb5167790057c0ae07b732;hb=1c87dd76c490041fce01e3dbfe29d993eadd693b;hp=3974e47d9315dcf2f75bc1e0d88719c34e4400bd;hpb=472d546054dadacca91530bad42ad06f6408124e;p=oweals%2Fu-boot.git

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 3974e47d93..0d2d9a4693 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -3,24 +3,7 @@
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  * Keith Outwater, keith_outwater@mvis.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
@@ -101,25 +84,26 @@
 #define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ/5	/* 200 ms */
 #endif
 
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
+			bitstream_type bstype)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
-		ret_val = Virtex2_ss_load (desc, buf, bsize);
+		ret_val = virtex2_ss_load(desc, buf, bsize);
 		break;
 
 	case slave_selectmap:
 		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_load (desc, buf, bsize);
+		ret_val = virtex2_ssm_load(desc, buf, bsize);
 		break;
 
 	default:
@@ -129,19 +113,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ss_dump (desc, buf, bsize);
+		ret_val = virtex2_ss_dump(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+		ret_val = virtex2_ssm_dump(desc, buf, bsize);
 		break;
 
 	default:
@@ -151,7 +135,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_info (Xilinx_desc * desc)
+static int virtex2_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -170,10 +154,10 @@ int Virtex2_info (Xilinx_desc * desc)
  *    INIT_B and DONE lines.  If both are high, configuration has
  *    succeeded. Congratulations!
  */
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
 			__FUNCTION__, __LINE__, fn);
@@ -369,10 +353,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 /*
  * Read the FPGA configuration data
  */
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	if (fn) {
 		unsigned char *data = (unsigned char *) buf;
@@ -421,16 +405,22 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
 /* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+	.load = virtex2_load,
+	.dump = virtex2_dump,
+	.info = virtex2_info,
+};