X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Ffpga%2Fsocfpga_arria10.c;h=dfd3cbb461028e8d77a228f31db9a2dac7949970;hb=c27178ba3649f539c9f1890ea147f4c5415f63b5;hp=5fb9d6a1911a1148ef5a634759ae5a8ca2d45783;hpb=a239147fa2c0c3fe849ccaffd72c4dc4cae2be71;p=oweals%2Fu-boot.git diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 5fb9d6a191..dfd3cbb461 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -2,6 +2,8 @@ /* * Copyright (C) 2017-2019 Intel Corporation */ +#include +#include #include #include #include @@ -16,6 +18,8 @@ #include #include #include +#include +#include #define CFGWDTH_32 1 #define MIN_BITSTREAM_SIZECHECK 230 @@ -30,9 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_fpga_manager *fpga_manager_base = (void *)SOCFPGA_FPGAMGRREGS_ADDRESS; -static const struct socfpga_system_manager *system_manager_base = - (void *)SOCFPGA_SYSMGR_ADDRESS; - static void fpgamgr_set_cd_ratio(unsigned long ratio); static uint32_t fpgamgr_get_msel(void) @@ -818,7 +819,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, } /* Disable all signals from HPS peripheral controller to FPGA */ - writel(0, &system_manager_base->fpgaintf_en_global); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL); /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(); @@ -910,7 +911,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) memset(&rbfinfo, 0, sizeof(rbfinfo)); /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &system_manager_base->fpgaintf_en_global); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL); /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset();