X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fddr%2Ffsl%2Fmpc85xx_ddr_gen3.c;h=ab8d2deaf9f490d1e53a7ea25d454a7e94815fa9;hb=60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22;hp=952b296dd8f7a18edd023b6d9a3bc816d21297f4;hpb=2a5d5d27edfbdb0e02a7fcf05569f92c02ae44ee;p=oweals%2Fu-boot.git

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 952b296dd8..ab8d2deaf9 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -4,9 +4,11 @@
  */
 
 #include <common.h>
+#include <log.h>
 #include <asm/io.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/processor.h>
+#include <linux/delay.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -370,8 +372,6 @@ step2:
 	debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 
 #endif	/* part 1 of the workaound */
-	/* Always start in self-refresh, clear after MEM_EN */
-	setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
 
 	/*
 	 * 500 painful micro-seconds must elapse between
@@ -384,6 +384,8 @@ step2:
 
 #ifdef CONFIG_DEEP_SLEEP
 	if (is_warm_boot()) {
+		/* enter self-refresh */
+		setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
 		/* do board specific memory setup */
 		board_mem_sleep_setup();
 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
@@ -395,10 +397,6 @@ step2:
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 	asm volatile("sync;isync");
 
-	/* Exit self-refresh after DDR conf as some ddr memories can fail. */
-	clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
-	asm volatile("sync;isync");
-
 	total_gb_size_per_controller = 0;
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (!(regs->cs[i].config & 0x80000000))
@@ -548,4 +546,9 @@ step2:
 		clrbits_be32(&ddr->sdram_cfg, 0x2);
 	}
 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
+#ifdef CONFIG_DEEP_SLEEP
+	if (is_warm_boot())
+		/* exit self-refresh */
+		clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
+#endif
 }