X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fddr%2Ffsl%2Fctrl_regs.c;h=8543679108751b1597137ecc8e859226d71fdb9b;hb=61bd2f75f5eaf645e2c90fe2294cba37f7d8627f;hp=9e2a4d2f467ee834078369344c2bf178c9d33f9c;hpb=b41411954d4ccf6ddaa581178462017557b82b5d;p=oweals%2Fu-boot.git

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9e2a4d2f46..8543679108 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -17,8 +17,6 @@
 #include <fsl_immap.h>
 #include <asm/io.h>
 
-unsigned int picos_to_mclk(unsigned int picos);
-
 /*
  * Determine Rtt value.
  *
@@ -78,10 +76,11 @@ static inline int fsl_ddr_get_rtt(void)
  *       16 for <= 2933MT/s
  *       18 for higher
  */
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+				const unsigned int ctrl_num)
 {
 	unsigned int cwl;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 	if (mclk_ps >= 1250)
 		cwl = 9;
 	else if (mclk_ps >= 1070)
@@ -111,10 +110,11 @@ static inline unsigned int compute_cas_write_latency(void)
  *       11 if 0.935ns > tCK >= 0.833ns
  *       12 if 0.833ns > tCK >= 0.75ns
  */
-static inline unsigned int compute_cas_write_latency(void)
+static inline unsigned int compute_cas_write_latency(
+				const unsigned int ctrl_num)
 {
 	unsigned int cwl;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 
 	if (mclk_ps >= 2500)
 		cwl = 5;
@@ -253,22 +253,30 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 
 #if !defined(CONFIG_SYS_FSL_DDR1)
+/*
+ * Check DIMM configuration, return 2 if quad-rank or two dual-rank
+ * Return 1 if other two slots configuration. Return 0 if single slot.
+ */
 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 {
 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 	if (dimm_params[0].n_ranks == 4)
-		return 1;
+		return 2;
 #endif
 
 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 	if ((dimm_params[0].n_ranks == 2) &&
 		(dimm_params[1].n_ranks == 2))
-		return 1;
+		return 2;
 
 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 	if (dimm_params[0].n_ranks == 4)
-		return 1;
+		return 2;
 #endif
+
+	if ((dimm_params[0].n_ranks != 0) &&
+	    (dimm_params[2].n_ranks != 0))
+		return 1;
 #endif
 	return 0;
 }
@@ -279,7 +287,8 @@ static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
  * Avoid writing for DDR I.  The new PQ38 DDR controller
  * dreams up non-zero default values to be backwards compatible.
  */
-static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_0(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const dimm_params_t *dimm_params)
 {
@@ -298,24 +307,29 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	/* Mode register set cycle time (tMRD). */
 	unsigned char tmrd_mclk;
 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
 	/* tXP=max(4nCK, 6ns) */
 	int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
-	trwt_mclk = 2;
+	unsigned int data_rate = get_ddr_freq(ctrl_num);
+
+	/* for faster clock, need more time for data setup */
+	trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 	twrt_mclk = 1;
-	act_pd_exit_mclk = picos_to_mclk(txp);
+	act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	/*
 	 * MRS_CYC = max(tMRD, tMOD)
 	 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 	 */
-	tmrd_mclk = max(24U, picos_to_mclk(15000));
+	tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	unsigned int data_rate = get_ddr_freq(0);
+	unsigned int data_rate = get_ddr_freq(ctrl_num);
 	int txp;
+	unsigned int ip_rev;
+	int odt_overlap;
 	/*
 	 * (tXARD and tXARDS). Empirical?
 	 * The DDR3 spec has not tXARD,
@@ -327,17 +341,46 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 
-	tmrd_mclk = 4;
+	ip_rev = fsl_ddr_get_version(ctrl_num);
+	if (ip_rev >= 0x40700) {
+		/*
+		 * MRS_CYC = max(tMRD, tMOD)
+		 * tMRD = 4nCK (8nCK for RDIMM)
+		 * tMOD = max(12nCK, 15ns)
+		 */
+		tmrd_mclk = max((unsigned int)12,
+				picos_to_mclk(ctrl_num, 15000));
+	} else {
+		/*
+		 * MRS_CYC = tMRD
+		 * tMRD = 4nCK (8nCK for RDIMM)
+		 */
+		if (popts->registered_dimm_en)
+			tmrd_mclk = 8;
+		else
+			tmrd_mclk = 4;
+	}
+
 	/* set the turnaround time */
 
 	/*
-	 * for single quad-rank DIMM and two dual-rank DIMMs
+	 * for single quad-rank DIMM and two-slot DIMMs
 	 * to avoid ODT overlap
 	 */
-	if (avoid_odt_overlap(dimm_params)) {
+	odt_overlap = avoid_odt_overlap(dimm_params);
+	switch (odt_overlap) {
+	case 2:
 		twwt_mclk = 2;
 		trrt_mclk = 1;
+		break;
+	case 1:
+		twwt_mclk = 1;
+		trrt_mclk = 0;
+		break;
+	default:
+		break;
 	}
+
 	/* for faster clock, need more time for data setup */
 	trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 
@@ -350,7 +393,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 		taxpd_mclk = 1;
 	} else {
 		/* act_pd_exit_mclk = tXARD, see above */
-		act_pd_exit_mclk = picos_to_mclk(txp);
+		act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 		/* Mode register MR0[A12] is '1' - fast exit */
 		pre_pd_exit_mclk = act_pd_exit_mclk;
 		taxpd_mclk = 1;
@@ -383,14 +426,15 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 		);
 	debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 }
-#endif	/* defined(CONFIG_SYS_FSL_DDR2) */
+#endif	/* !defined(CONFIG_SYS_FSL_DDR1) */
 
 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
-static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency)
+static void set_timing_cfg_3(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency,
+			     unsigned int additive_latency)
 {
 	/* Extended precharge to activate interval (tRP) */
 	unsigned int ext_pretoact = 0;
@@ -409,18 +453,18 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 	/* Control Adjust */
 	unsigned int cntl_adj = 0;
 
-	ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
-	ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
-	ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
+	ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
+	ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
+	ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 	ext_caslat = (2 * cas_latency - 1) >> 4;
 	ext_add_lat = additive_latency >> 4;
 #ifdef CONFIG_SYS_FSL_DDR4
-	ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 #else
-	ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 #endif
-	ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+	ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 		(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 
 	ddr->timing_cfg_3 = (0
@@ -437,10 +481,11 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
-static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency)
+static void set_timing_cfg_1(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency)
 {
 	/* Precharge-to-activate interval (tRP) */
 	unsigned char pretoact_mclk;
@@ -472,9 +517,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 		1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 #endif
 
-	pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
-	acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
-	acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
+	pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
+	acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
+	acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 
 	/*
 	 * Translate CAS Latency to a DDR controller field value:
@@ -502,26 +547,26 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 	 * we need set extend bit for it at
 	 * TIMING_CFG_3[EXT_CASLAT]
 	 */
-	if (fsl_ddr_get_version() <= 0x40400)
+	if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 		caslat_ctrl = 2 * cas_latency - 1;
 	else
 		caslat_ctrl = (cas_latency - 1) << 1;
 #endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
-	refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-	acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
-	wrtord_mclk = max(2U, picos_to_mclk(2500));
+	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
+	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+	acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
+	wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 	if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 		printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 	else
 		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 #else
-	refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
-	acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
-	wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
+	refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
+	wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
+	acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
+	wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 	if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 		printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 	else
@@ -564,11 +609,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
-static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm,
-			       unsigned int cas_latency,
-			       unsigned int additive_latency)
+static void set_timing_cfg_2(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const memctl_options_t *popts,
+			     const common_timing_params_t *common_dimm,
+			     unsigned int cas_latency,
+			     unsigned int additive_latency)
 {
 	/* Additive latency */
 	unsigned char add_lat_mclk;
@@ -585,7 +631,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	/* Window for four activates (tFAW) */
 	unsigned short four_act;
 #ifdef CONFIG_SYS_FSL_DDR3
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 #endif
 
 	/* FIXME add check that this must be less than acttorw_mclk */
@@ -603,13 +649,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #elif defined(CONFIG_SYS_FSL_DDR2)
 	wr_lat = cas_latency - 1;
 #else
-	wr_lat = compute_cas_write_latency();
+	wr_lat = compute_cas_write_latency(ctrl_num);
 #endif
 
 #ifdef CONFIG_SYS_FSL_DDR4
-	rd_to_pre = picos_to_mclk(7500);
+	rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 #else
-	rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
+	rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 #endif
 	/*
 	 * JEDEC has some min requirements for tRTP
@@ -627,19 +673,20 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	wr_data_delay = popts->write_data_delay;
 #ifdef CONFIG_SYS_FSL_DDR4
 	cpo = 0;
-	cke_pls = max(3U, picos_to_mclk(5000));
+	cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 #elif defined(CONFIG_SYS_FSL_DDR3)
 	/*
 	 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 	 *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 	 *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 	 */
-	cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
-				       (mclk_ps > 1245 ? 5625 : 5000)));
+	cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
+					(mclk_ps > 1245 ? 5625 : 5000)));
 #else
 	cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 #endif
-	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
+	four_act = picos_to_mclk(ctrl_num,
+				 popts->tfaw_window_four_activates_ps);
 
 	ddr->timing_cfg_2 = (0
 		| ((add_lat_mclk & 0xf) << 28)
@@ -780,7 +827,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
-static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const unsigned int unq_mrs_en)
 {
@@ -810,7 +858,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 			break;
 		}
 	}
-
+	sr_ie = popts->self_refresh_interrupt_en;
 	num_pr = 1;	/* Make this configurable */
 
 	/*
@@ -827,7 +875,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #endif
 
 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
-	slow = get_ddr_freq(0) < 1249000000;
+	slow = get_ddr_freq(ctrl_num) < 1249000000;
 #endif
 
 	if (popts->registered_dimm_en) {
@@ -877,7 +925,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 
 #ifdef CONFIG_SYS_FSL_DDR4
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -888,10 +937,10 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int wr_crc = 0;	/* Disable */
 	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
 	unsigned int srt = 0;	/* self-refresh temerature, normal range */
-	unsigned int cwl = compute_cas_write_latency() - 9;
+	unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 	unsigned int mpr = 0;	/* serial */
 	unsigned int wc_lat;
-	const unsigned int mclk_ps = get_memory_clk_period_ps();
+	const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 
 	if (popts->rtt_override)
 		rtt_wr = popts->rtt_wr_override_value;
@@ -964,7 +1013,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 }
 #elif defined(CONFIG_SYS_FSL_DDR3)
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -975,7 +1025,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
 	unsigned int srt = 0;	/* self-refresh temerature, normal range */
 	unsigned int asr = 0;	/* auto self-refresh disable */
-	unsigned int cwl = compute_cas_write_latency() - 5;
+	unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
 	unsigned int pasr = 0;	/* partial array self refresh disable */
 
 	if (popts->rtt_override)
@@ -1039,7 +1089,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 
 #else /* for DDR2 and DDR1 */
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1065,16 +1116,32 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 	int i;
 	unsigned short esdmode4 = 0;	/* Extended SDRAM mode 4 */
 	unsigned short esdmode5;	/* Extended SDRAM mode 5 */
+	int rtt_park = 0;
 
-	esdmode5 = 0x00000400;		/* Data mask enabled */
+	if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
+		esdmode5 = 0x00000500;	/* Data mask enable, RTT_PARK CS0 */
+		rtt_park = 1;
+	} else {
+		esdmode5 = 0x00000400;	/* Data mask enabled */
+	}
 
 	ddr->ddr_sdram_mode_9 = (0
 				 | ((esdmode4 & 0xffff) << 16)
 				 | ((esdmode5 & 0xffff) << 0)
 				);
+
+	/* only mode_9 use 0x500, others use 0x400 */
+
 	debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
 	if (unq_mrs_en) {	/* unique mode registers are supported */
 		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+			if (!rtt_park &&
+			    (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
+				esdmode5 |= 0x00000500;	/* RTT_PARK */
+				rtt_park = 1;
+			} else {
+				esdmode5 = 0x00000400;
+			}
 			switch (i) {
 			case 1:
 				ddr->ddr_sdram_mode_11 = (0
@@ -1106,7 +1173,8 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
-static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
 				const memctl_options_t *popts,
 				const common_timing_params_t *common_dimm,
 				const unsigned int unq_mrs_en)
@@ -1114,7 +1182,7 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
 	int i;
 	unsigned short esdmode6 = 0;	/* Extended SDRAM mode 6 */
 	unsigned short esdmode7 = 0;	/* Extended SDRAM mode 7 */
-	unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
+	unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
 
 	esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
 
@@ -1158,14 +1226,15 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
 #endif
 
 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
-static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
-			       const memctl_options_t *popts,
-			       const common_timing_params_t *common_dimm)
+static void set_ddr_sdram_interval(const unsigned int ctrl_num,
+				fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts,
+				const common_timing_params_t *common_dimm)
 {
 	unsigned int refint;	/* Refresh interval */
 	unsigned int bstopre;	/* Precharge interval */
 
-	refint = picos_to_mclk(common_dimm->refresh_rate_ps);
+	refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
 
 	bstopre = popts->bstopre;
 
@@ -1179,7 +1248,8 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
 
 #ifdef CONFIG_SYS_FSL_DDR4
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1254,7 +1324,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	 * 1=fast exit DLL on (tXP)
 	 */
 
-	wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 	if (wr_mclk <= 24) {
 		wr = wr_table[wr_mclk - 10];
 	} else {
@@ -1349,7 +1419,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 
 #elif defined(CONFIG_SYS_FSL_DDR3)
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1428,7 +1499,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	dll_on = 1;
 
-	wr_mclk = picos_to_mclk(common_dimm->twr_ps);
+	wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 	if (wr_mclk <= 16) {
 		wr = wr_table[wr_mclk - 5];
 	} else {
@@ -1544,7 +1615,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #else /* !CONFIG_SYS_FSL_DDR3 */
 
 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
-static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
+static void set_ddr_sdram_mode(const unsigned int ctrl_num,
+			       fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm,
 			       unsigned int cas_latency,
@@ -1616,7 +1688,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_SYS_FSL_DDR1)
 	wr = 0;       /* Historical */
 #elif defined(CONFIG_SYS_FSL_DDR2)
-	wr = picos_to_mclk(common_dimm->twr_ps);
+	wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 #endif
 	dll_res = 0;
 	mode = 0;
@@ -1694,9 +1766,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 					 const memctl_options_t *popts)
 {
 	unsigned int clk_adjust;	/* Clock adjust */
+	unsigned int ss_en = 0;		/* Source synchronous enable */
 
+#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+	/* Per FSL Application Note: AN2805 */
+	ss_en = 1;
+#endif
 	clk_adjust = popts->clk_adjust;
-	ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
+	ddr->ddr_sdram_clk_cntl = (0
+				   | ((ss_en & 0x1) << 31)
+				   | ((clk_adjust & 0xF) << 23)
+				   );
 	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
 
@@ -1804,15 +1884,16 @@ static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
 	debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
 }
 
-static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
-			const common_timing_params_t *common_dimm)
+static void set_timing_cfg_7(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
+			     const common_timing_params_t *common_dimm)
 {
 	unsigned int txpr, tcksre, tcksrx;
 	unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
 
-	txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
-	tcksre = max(5U, picos_to_mclk(10000));
-	tcksrx = max(5U, picos_to_mclk(10000));
+	txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
+	tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
+	tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
 	par_lat = 0;
 	cs_to_cmd = 0;
 
@@ -1845,14 +1926,15 @@ static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
 	debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
 }
 
-static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
+static void set_timing_cfg_8(const unsigned int ctrl_num,
+			     fsl_ddr_cfg_regs_t *ddr,
 			     const memctl_options_t *popts,
 			     const common_timing_params_t *common_dimm,
 			     unsigned int cas_latency)
 {
 	unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
 	unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
-	unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
+	unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
 	unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
 			      ((ddr->timing_cfg_2 & 0x00040000) >> 14);
 
@@ -1873,11 +1955,11 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
 		wwt_bg = tccdl - 4;
 	} else {
 		rrt_bg = tccdl - 2;
-		wwt_bg = tccdl - 4;
+		wwt_bg = tccdl - 2;
 	}
 
-	acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
-	wrtord_bg = max(4U, picos_to_mclk(7500));
+	acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
+	wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
 	if (popts->otf_burst_chop_en)
 		wrtord_bg += 2;
 
@@ -1907,31 +1989,41 @@ static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
 			       const dimm_params_t *dimm_params)
 {
 	unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
+	int i;
 
-	ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
-			((dimm_params->dq_mapping[1] & 0x3F) << 20) |
-			((dimm_params->dq_mapping[2] & 0x3F) << 14) |
-			((dimm_params->dq_mapping[3] & 0x3F) << 8) |
-			((dimm_params->dq_mapping[4] & 0x3F) << 2);
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (dimm_params[i].n_ranks)
+			break;
+	}
+	if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
+		puts("DDR error: no DIMM found!\n");
+		return;
+	}
+
+	ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
+			((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
+			((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
+			((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
+			((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
 
-	ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
-			((dimm_params->dq_mapping[6] & 0x3F) << 20) |
-			((dimm_params->dq_mapping[7] & 0x3F) << 14) |
-			((dimm_params->dq_mapping[10] & 0x3F) << 8) |
-			((dimm_params->dq_mapping[11] & 0x3F) << 2);
+	ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
+			((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
+			((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
+			((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
+			((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
 
-	ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
-			((dimm_params->dq_mapping[13] & 0x3F) << 20) |
-			((dimm_params->dq_mapping[14] & 0x3F) << 14) |
-			((dimm_params->dq_mapping[15] & 0x3F) << 8) |
-			((dimm_params->dq_mapping[16] & 0x3F) << 2);
+	ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
+			((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
+			((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
+			((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
+			((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
 
 	/* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
-	ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
-			((dimm_params->dq_mapping[8] & 0x3F) << 20) |
+	ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
+			((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
 			(acc_ecc_en ? 0 :
-			 (dimm_params->dq_mapping[9] & 0x3F) << 14) |
-			dimm_params->dq_mapping_ors;
+			 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
+			dimm_params[i].dq_mapping_ors;
 
 	debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
 	debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
@@ -2109,7 +2201,8 @@ check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 }
 
 unsigned int
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+			       const memctl_options_t *popts,
 			       fsl_ddr_cfg_regs_t *ddr,
 			       const common_timing_params_t *common_dimm,
 			       const dimm_params_t *dimm_params,
@@ -2281,34 +2374,34 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_eor(ddr, popts);
 
 #if !defined(CONFIG_SYS_FSL_DDR1)
-	set_timing_cfg_0(ddr, popts, dimm_params);
+	set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
 #endif
 
-	set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
+	set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
 			 additive_latency);
-	set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
-	set_timing_cfg_2(ddr, popts, common_dimm,
-				cas_latency, additive_latency);
+	set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
+	set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
+			 cas_latency, additive_latency);
 
 	set_ddr_cdr1(ddr, popts);
 	set_ddr_cdr2(ddr, popts);
 	set_ddr_sdram_cfg(ddr, popts, common_dimm);
-	ip_rev = fsl_ddr_get_version();
+	ip_rev = fsl_ddr_get_version(ctrl_num);
 	if (ip_rev > 0x40400)
 		unq_mrs_en = 1;
 
 	if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
 		ddr->debug[18] = popts->cswl_override;
 
-	set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
-	set_ddr_sdram_mode(ddr, popts, common_dimm,
-				cas_latency, additive_latency, unq_mrs_en);
-	set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
+	set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
+	set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
+			   cas_latency, additive_latency, unq_mrs_en);
+	set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
 #ifdef CONFIG_SYS_FSL_DDR4
 	set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
-	set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
+	set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
 #endif
-	set_ddr_sdram_interval(ddr, popts, common_dimm);
+	set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
 	set_ddr_data_init(ddr);
 	set_ddr_sdram_clk_cntl(ddr, popts);
 	set_ddr_init_addr(ddr);
@@ -2318,8 +2411,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 #ifdef CONFIG_SYS_FSL_DDR4
 	set_ddr_sdram_cfg_3(ddr, popts);
 	set_timing_cfg_6(ddr);
-	set_timing_cfg_7(ddr, common_dimm);
-	set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
+	set_timing_cfg_7(ctrl_num, ddr, common_dimm);
+	set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
 	set_timing_cfg_9(ddr);
 	set_ddr_dq_mapping(ddr, dimm_params);
 #endif
@@ -2334,7 +2427,11 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 #ifdef CONFIG_SYS_FSL_DDR_EMU
 	/* disble DDR training for emulator */
 	ddr->debug[2] = 0x00000400;
-	ddr->debug[4] = 0xff800000;
+	ddr->debug[4] = 0xff800800;
+	ddr->debug[5] = 0x08000800;
+	ddr->debug[6] = 0x08000800;
+	ddr->debug[7] = 0x08000800;
+	ddr->debug[8] = 0x08000800;
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
 	if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))