X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=drivers%2Fddr%2Faltera%2Fsequencer.h;h=3e4152f69f8a033310e5668fd39769a47af804f6;hb=49891df661acf164460ba3ada60fccfc5a53ea71;hp=ed2bae2c5d8274dd6775fc71df88cd0b09efe0f4;hpb=3da428595e861f90ff0d6687cedff3056f7c7890;p=oweals%2Fu-boot.git

diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index ed2bae2c5d..3e4152f69f 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -16,17 +16,16 @@
 	/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
 #define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
 
-#define RW_MGR_RUN_SINGLE_GROUP	(BASE_RW_MGR)
-#define RW_MGR_RUN_ALL_GROUPS	(BASE_RW_MGR + 0x0400)
-
-#define RW_MGR_DI_BASE		(BASE_RW_MGR + 0x0020)
+#define RW_MGR_RUN_SINGLE_GROUP_OFFSET		0x0
+#define RW_MGR_RUN_ALL_GROUPS_OFFSET		0x0400
+#define RW_MGR_RESET_READ_DATAPATH_OFFSET	0x1000
+#define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET	0x1400
+#define RW_MGR_INST_ROM_WRITE_OFFSET		0x1800
+#define RW_MGR_AC_ROM_WRITE_OFFSET		0x1C00
 
 #define RW_MGR_MEM_NUMBER_OF_RANKS	1
 #define NUM_SHADOW_REGS			1
 
-#define RW_MGR_RESET_READ_DATAPATH	(BASE_RW_MGR + 0x1000)
-#define RW_MGR_SET_CS_AND_ODT_MASK	(BASE_RW_MGR + 0x1400)
-
 #define RW_MGR_RANK_NONE		0xFF
 #define RW_MGR_RANK_ALL			0x00
 
@@ -78,42 +77,27 @@
 /* length of VFIFO, from SW_MACROS */
 #define VFIFO_SIZE			(READ_VALID_FIFO_SIZE)
 
-/* MarkW: how should these base addresses be done for A-V? */
-#define BASE_PTR_MGR			0x00040000
-#define BASE_SCC_MGR			0x00058000
-#define BASE_REG_FILE			0x00070000
-#define BASE_TIMER			0x00078000
-#define BASE_PHY_MGR			0x00088000
-#define BASE_RW_MGR			0x00090000
-#define BASE_DATA_MGR			0x00098000
-#define BASE_MMR			0x000C0000
-#define BASE_TRK_MGR			0x000D0000
-
-#define SCC_MGR_GROUP_COUNTER			(BASE_SCC_MGR + 0x0000)
-#define SCC_MGR_DQS_IN_DELAY			(BASE_SCC_MGR + 0x0100)
-#define SCC_MGR_DQS_EN_PHASE			(BASE_SCC_MGR + 0x0200)
-#define SCC_MGR_DQS_EN_DELAY			(BASE_SCC_MGR + 0x0300)
-#define SCC_MGR_DQDQS_OUT_PHASE			(BASE_SCC_MGR + 0x0400)
-#define SCC_MGR_OCT_OUT1_DELAY			(BASE_SCC_MGR + 0x0500)
-#define SCC_MGR_IO_OUT1_DELAY			(BASE_SCC_MGR + 0x0700)
-#define SCC_MGR_IO_IN_DELAY			(BASE_SCC_MGR + 0x0900)
+#define SCC_MGR_GROUP_COUNTER_OFFSET		0x0000
+#define SCC_MGR_DQS_IN_DELAY_OFFSET		0x0100
+#define SCC_MGR_DQS_EN_PHASE_OFFSET		0x0200
+#define SCC_MGR_DQS_EN_DELAY_OFFSET		0x0300
+#define SCC_MGR_DQDQS_OUT_PHASE_OFFSET		0x0400
+#define SCC_MGR_OCT_OUT1_DELAY_OFFSET		0x0500
+#define SCC_MGR_IO_OUT1_DELAY_OFFSET		0x0700
+#define SCC_MGR_IO_IN_DELAY_OFFSET		0x0900
 
 /* HHP-HPS-specific versions of some commands */
-#define SCC_MGR_DQS_EN_DELAY_GATE		(BASE_SCC_MGR + 0x0600)
-#define SCC_MGR_IO_OE_DELAY			(BASE_SCC_MGR + 0x0800)
-#define SCC_MGR_HHP_GLOBALS			(BASE_SCC_MGR + 0x0A00)
-#define SCC_MGR_HHP_RFILE			(BASE_SCC_MGR + 0x0B00)
-#define SCC_MGR_AFI_CAL_INIT			(BASE_SCC_MGR + 0x0D00)
-
-#define SDR_PHYGRP_SCCGRP_ADDRESS		0x0
-#define SDR_PHYGRP_PHYMGRGRP_ADDRESS		0x1000
-#define SDR_PHYGRP_RWMGRGRP_ADDRESS		0x2000
-#define SDR_PHYGRP_DATAMGRGRP_ADDRESS		0x4000
-#define SDR_PHYGRP_REGFILEGRP_ADDRESS		0x4800
-
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
+#define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET	0x0600
+#define SCC_MGR_IO_OE_DELAY_OFFSET		0x0800
+#define SCC_MGR_HHP_GLOBALS_OFFSET		0x0A00
+#define SCC_MGR_HHP_RFILE_OFFSET		0x0B00
+#define SCC_MGR_AFI_CAL_INIT_OFFSET		0x0D00
+
+#define SDR_PHYGRP_SCCGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x0)
+#define SDR_PHYGRP_PHYMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x1000)
+#define SDR_PHYGRP_RWMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x2000)
+#define SDR_PHYGRP_DATAMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4000)
+#define SDR_PHYGRP_REGFILEGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4800)
 
 #define PHY_MGR_CAL_RESET		(0)
 #define PHY_MGR_CAL_SUCCESS		(1)
@@ -195,9 +179,6 @@
 #define SEQ_TRESET_CNTR2_VAL 131
 #endif
 
-#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
-#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
-
 struct socfpga_sdr_rw_load_manager {
 	u32	load_cntr0;
 	u32	load_cntr1;
@@ -261,10 +242,6 @@ struct gbl_type {
 
 	uint32_t curr_read_lat;
 
-	/* current write latency */
-
-	uint32_t curr_write_lat;
-
 	/* error code */
 
 	uint32_t error_substage;